Novel methods for the interface between the simulation and hardware of Power Hardware-In-the-Loop (PHIL) configurations have been analysed, developed and experimentally evaluated in this thesis, for enhancing the applicability of PHIL simulations, increasing its stability and accuracy performance.Time delay is proven to be a critical limiting factor for PHIL simulations. Appropriately, a characterisation methodology for the time delay present within PHIL has been established, by which individual identification of time delay sources as well as time delay dynamics within the different components are reviewed. As a result, variable time delay has been identified within these configurations and mitigation techniques for the time delay and its variability are presented.Furthermore, a time delay compensation scheme using Sliding Discrete Fourier Transform (SDFT) is demonstrated experimentally to improve the accuracy and stability of PHIL, even when harmonic components are present.Detailed stability analysis of PHIL simulations performed provides clarification on the stability conditions of Ideal Transformer Method (ITM) Interface Algorithms (IAs). Additional improvements to PHIL IAs have been evaluated, with novel adaptive IAs established to provide enhanced stability.Finally, enhancement of applicability of PHIL simulations is also experimentally proven with the implementation of an initialization process to a large scale power system application, in which the time delay compensation algorithm is also integrated.
|Date of Award||1 Oct 2016|
- University Of Strathclyde
|Sponsors||University of Strathclyde|
|Supervisor||Graeme Burt (Supervisor) & (Supervisor)|