The use of low-cost CubeSats in the context of satellite formation flying appears favourable due to their small size, relatively low launch cost, short development cycle and utilisation of commercial off the shelf components. However, the task of managing complex formations using a large number of satellites in Earth orbit is not a trivial one, and is further exacerbated by low-power and processing constraints in CubeSats. With this in mind, a Field Programmable Gate Array (FPGA) based system has been developed to provide next generation on-board computing capability.The features and functionality provided by this on-board computer, as well as the steps taken to ensure reliability, including design processes and mitigation techniques are presented in this work and compared to state of the art technology. Coupling reliable formation flying capabilities with the possibility of producing complex patterns using spacecraft will enable the potential of grouping a number of antenna elements into a cooperative structure. The key point in the exploitation of formation flying techniques for the deployment of an antenna array is that the performance of a homogeneous pattern of array elements can be matched or surpassed by fractal geometries.This thesis analyses the Purina fractal array when utilised for beamforming. A new metric termed power concentration is introduced, which assesses the power dissipated within a cone aligned with the array's look direction, i.e. an assessment how much of the radiated power will reach a specific foot print. Using this metric the performance for beamformers of varying complexity can be compared, independent of the number of sensor elements used to form the array and across a range of frequencies. Furthermore the robustness of the array with respect to element displacement and failure is investigated.The fractionated nature of such a satellite network and the low-power nature of the nodes motivates distributed processing when using such an array as a beamformer. By mirroring the fractal structure in the processing architecture, the proposed idea demonstrates that benefits such as strictly limited local processing capability independent of the array’s dimension and local calibration can be bought at the expense of a slightly increased overall cost.
|Date of Award||26 May 2017|
- University Of Strathclyde
|Sponsors||EPSRC (Engineering and Physical Sciences Research Council)|
|Supervisor||Robert Stewart (Supervisor) & Stephan Weiss (Supervisor)|