Via hole technology for thin-film transistor circuits

H. Gleskova, S. Wagner, Q. Zhang, D. S. Shen

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.

LanguageEnglish
Pages523-525
Number of pages3
JournalIEEE Electron Device Letters
Volume18
Issue number11
DOIs
Publication statusPublished - 1997

Fingerprint

Thin film transistors
Networks (circuits)
Amorphous silicon
Liquid crystal displays
Display devices
Glass
Lasers
Substrates

Keywords

  • hole technology
  • film transistor circuits
  • thin-film transistor

Cite this

Gleskova, H. ; Wagner, S. ; Zhang, Q. ; Shen, D. S. / Via hole technology for thin-film transistor circuits. In: IEEE Electron Device Letters . 1997 ; Vol. 18, No. 11. pp. 523-525.
@article{19835ffd7d994a0a93856b5e14a248f0,
title = "Via hole technology for thin-film transistor circuits",
abstract = "We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.",
keywords = "hole technology, film transistor circuits, thin-film transistor",
author = "H. Gleskova and S. Wagner and Q. Zhang and Shen, {D. S.}",
year = "1997",
doi = "10.1109/55.641433",
language = "English",
volume = "18",
pages = "523--525",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
number = "11",

}

Via hole technology for thin-film transistor circuits. / Gleskova, H.; Wagner, S.; Zhang, Q.; Shen, D. S.

In: IEEE Electron Device Letters , Vol. 18, No. 11, 1997, p. 523-525.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Via hole technology for thin-film transistor circuits

AU - Gleskova, H.

AU - Wagner, S.

AU - Zhang, Q.

AU - Shen, D. S.

PY - 1997

Y1 - 1997

N2 - We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.

AB - We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.

KW - hole technology

KW - film transistor circuits

KW - thin-film transistor

UR - http://www.scopus.com/inward/record.url?scp=0031272055&partnerID=8YFLogxK

U2 - 10.1109/55.641433

DO - 10.1109/55.641433

M3 - Article

VL - 18

SP - 523

EP - 525

JO - IEEE Electron Device Letters

T2 - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 11

ER -