Via hole technology for thin-film transistor circuits

H. Gleskova, S. Wagner, Q. Zhang, D. S. Shen

Research output: Contribution to journalArticlepeer-review

13 Citations (Scopus)


We analyze and demonstrate a new technique for reducing the gate RC delay of the amorphous silicon thin-film transistor (TFT) backplane of active matrix liquid crystal displays. The TFT gate line is driven from a bus on the back side of the glass substrate, through a laser-drilled via hole. Analysis shows that a few via holes suffice to considerably reduce the gate RC delay, or enable an equivalent increase in display size.

Original languageEnglish
Pages (from-to)523-525
Number of pages3
JournalIEEE Electron Device Letters
Issue number11
Publication statusPublished - 1997


  • hole technology
  • film transistor circuits
  • thin-film transistor


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