Via hole addressed TFT and process for large-area a-Si:H electronics

Helena Gleskova; S. Wagner; D. Shen

Via hole addressed TFT and process for large-area a-Si:H electronics

Helena Gleskova, S. Wagner, D. Shen

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

Abstract

We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. AU gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 mu m in 50 mu m glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.

Original language	English
Title of host publication	Amorphous and Microcrystalline Silicon Technology - 1997
Editors	S. Wagner, M. Hack, E. A. Schiff, R. Schropp, I. Shimizu
Pages	869-874
Number of pages	6
Volume	467
Publication status	Published - 1997
Event	Symposium on Amorphous and Microcrystalline Silicon Technology - San Francisco, United States Duration: 31 Mar 1997 → 4 Apr 1997

Publication series

Name	MRS Symposium Proceedings
Publisher	Materials Research Society
Volume	467

Conference

Conference	Symposium on Amorphous and Microcrystalline Silicon Technology
Country/Territory	United States
City	San Francisco
Period	31/03/97 → 4/04/97

Keywords

RC gate delay reduction
amorphous silicon
thin-film transistors
thin glass substrate

Cite this

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title = "Via hole addressed TFT and process for large-area a-Si:H electronics",

abstract = "We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. AU gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 mu m in 50 mu m glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.",

keywords = "RC gate delay reduction, amorphous silicon, thin-film transistors, thin glass substrate",

author = "Helena Gleskova and S. Wagner and D. Shen",

year = "1997",

language = "English",

isbn = "1558993711 ",

volume = "467",

series = "MRS Symposium Proceedings",

publisher = "Materials Research Society ",

pages = "869--874",

editor = "S. Wagner and M. Hack and Schiff, {E. A.} and R. Schropp and I. Shimizu",

booktitle = "Amorphous and Microcrystalline Silicon Technology - 1997",

note = "Symposium on Amorphous and Microcrystalline Silicon Technology ; Conference date: 31-03-1997 Through 04-04-1997",

}

Gleskova, H, Wagner, S & Shen, D 1997, Via hole addressed TFT and process for large-area a-Si:H electronics. in S Wagner, M Hack, EA Schiff, R Schropp & I Shimizu (eds), Amorphous and Microcrystalline Silicon Technology - 1997. vol. 467, MRS Symposium Proceedings, vol. 467, pp. 869-874, Symposium on Amorphous and Microcrystalline Silicon Technology , San Francisco, United States, 31/03/97.

Via hole addressed TFT and process for large-area a-Si:H electronics. / Gleskova, Helena; Wagner, S.; Shen, D.
Amorphous and Microcrystalline Silicon Technology - 1997. ed. / S. Wagner; M. Hack; E. A. Schiff; R. Schropp; I. Shimizu. Vol. 467 1997. p. 869-874 (MRS Symposium Proceedings; Vol. 467).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

TY - GEN

T1 - Via hole addressed TFT and process for large-area a-Si:H electronics

AU - Gleskova, Helena

AU - Wagner, S.

AU - Shen, D.

PY - 1997

Y1 - 1997

N2 - We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. AU gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 mu m in 50 mu m glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.

AB - We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. AU gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 mu m in 50 mu m glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.

KW - RC gate delay reduction

KW - amorphous silicon

KW - thin-film transistors

KW - thin glass substrate

M3 - Conference contribution book

SN - 1558993711

VL - 467

T3 - MRS Symposium Proceedings

SP - 869

EP - 874

BT - Amorphous and Microcrystalline Silicon Technology - 1997

A2 - Wagner, S.

A2 - Hack, M.

A2 - Schiff, E. A.

A2 - Schropp, R.

A2 - Shimizu, I.

T2 - Symposium on Amorphous and Microcrystalline Silicon Technology

Y2 - 31 March 1997 through 4 April 1997

ER -

Via hole addressed TFT and process for large-area a-Si:H electronics

Abstract

Publication series

Conference

Keywords

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