Via hole addressed TFT and process for large-area a-Si:H electronics

Helena Gleskova, S. Wagner, D. Shen

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

Abstract

We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. AU gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 mu m in 50 mu m glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.
LanguageEnglish
Title of host publicationAmorphous and Microcrystalline Silicon Technology - 1997
EditorsS. Wagner, M. Hack, E. A. Schiff, R. Schropp, I. Shimizu
Pages869-874
Number of pages6
Volume467
Publication statusPublished - 1997
EventSymposium on Amorphous and Microcrystalline Silicon Technology - San Francisco, United States
Duration: 31 Mar 19974 Apr 1997

Publication series

NameMRS Symposium Proceedings
PublisherMaterials Research Society
Volume467

Conference

ConferenceSymposium on Amorphous and Microcrystalline Silicon Technology
CountryUnited States
CitySan Francisco
Period31/03/974/04/97

Fingerprint

electronics
glass
amorphous silicon
foils
transistors
masks
thin films
metals

Keywords

  • RC gate delay reduction
  • amorphous silicon
  • thin-film transistors
  • thin glass substrate

Cite this

Gleskova, H., Wagner, S., & Shen, D. (1997). Via hole addressed TFT and process for large-area a-Si:H electronics. In S. Wagner, M. Hack, E. A. Schiff, R. Schropp, & I. Shimizu (Eds.), Amorphous and Microcrystalline Silicon Technology - 1997 (Vol. 467, pp. 869-874). (MRS Symposium Proceedings; Vol. 467).
Gleskova, Helena ; Wagner, S. ; Shen, D. / Via hole addressed TFT and process for large-area a-Si:H electronics. Amorphous and Microcrystalline Silicon Technology - 1997. editor / S. Wagner ; M. Hack ; E. A. Schiff ; R. Schropp ; I. Shimizu. Vol. 467 1997. pp. 869-874 (MRS Symposium Proceedings).
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abstract = "We demonstrate a new technology for RC gate delay reduction, by fabricating an array of amorphous silicon thin-film transistors (a-Si:H TFTs) on a thin glass substrate provided with via holes. AU gates are connected through via holes to a metal line that is run on the back side of the substrate. We opened via holes with a diameter of 35 to 50 mu m in 50 mu m glass foil. For the first time, all TFT pattern definition steps used a process which employs electrophotographic toner masks.",
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author = "Helena Gleskova and S. Wagner and D. Shen",
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Gleskova, H, Wagner, S & Shen, D 1997, Via hole addressed TFT and process for large-area a-Si:H electronics. in S Wagner, M Hack, EA Schiff, R Schropp & I Shimizu (eds), Amorphous and Microcrystalline Silicon Technology - 1997. vol. 467, MRS Symposium Proceedings, vol. 467, pp. 869-874, Symposium on Amorphous and Microcrystalline Silicon Technology , San Francisco, United States, 31/03/97.

Via hole addressed TFT and process for large-area a-Si:H electronics. / Gleskova, Helena; Wagner, S.; Shen, D.

Amorphous and Microcrystalline Silicon Technology - 1997. ed. / S. Wagner; M. Hack; E. A. Schiff; R. Schropp; I. Shimizu. Vol. 467 1997. p. 869-874 (MRS Symposium Proceedings; Vol. 467).

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

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Gleskova H, Wagner S, Shen D. Via hole addressed TFT and process for large-area a-Si:H electronics. In Wagner S, Hack M, Schiff EA, Schropp R, Shimizu I, editors, Amorphous and Microcrystalline Silicon Technology - 1997. Vol. 467. 1997. p. 869-874. (MRS Symposium Proceedings).