This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized.
|Publication status||Published - 2002|
|Event||ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays - Monterey, California, United States|
Duration: 24 Feb 2002 → 26 Feb 2002
|Conference||ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays|
|Period||24/02/02 → 26/02/02|
- timing verification
- dynamically reconfigurable logic
- Xilinx Virtex
- FPGA series
Robertson, I., Irvine, J., Lysaght, P., & Robinson, D. (2002). Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series. Paper presented at ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays, Monterey, California, United States.