Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

I. Robertson, J. Irvine, P. Lysaght, D. Robinson

Research output: Contribution to conferencePaper

Abstract

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized.

Conference

ConferenceACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays
CountryUnited States
CityMonterey, California
Period24/02/0226/02/02

Fingerprint

Field programmable gate arrays (FPGA)
Computer aided design
Dynamical systems
Logic design
Switching circuits
Computer hardware description languages
Hardware

Keywords

  • timing verification
  • dynamically reconfigurable logic
  • Xilinx Virtex
  • FPGA series

Cite this

Robertson, I., Irvine, J., Lysaght, P., & Robinson, D. (2002). Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series. Paper presented at ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays, Monterey, California, United States.
Robertson, I. ; Irvine, J. ; Lysaght, P. ; Robinson, D. / Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series. Paper presented at ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays, Monterey, California, United States.
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author = "I. Robertson and J. Irvine and P. Lysaght and D. Robinson",
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Robertson, I, Irvine, J, Lysaght, P & Robinson, D 2002, 'Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series' Paper presented at ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays, Monterey, California, United States, 24/02/02 - 26/02/02, .

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series. / Robertson, I.; Irvine, J.; Lysaght, P.; Robinson, D.

2002. Paper presented at ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays, Monterey, California, United States.

Research output: Contribution to conferencePaper

TY - CONF

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AU - Robertson, I.

AU - Irvine, J.

AU - Lysaght, P.

AU - Robinson, D.

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N2 - This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized.

AB - This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized.

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KW - FPGA series

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Robertson I, Irvine J, Lysaght P, Robinson D. Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series. 2002. Paper presented at ACM/SIGDA 10th International Symposium on Field Programmable Gate Arrays, Monterey, California, United States.