The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

S. Loddick, U. Mupambireyi, S. Blair, C. Booth, X. Li, Andrew J. Roscoe, K. Daffey, L.J.W. Rn

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Abstract

Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs).

Original languageEnglish
Title of host publicationPower electronics and applications (EPE 2011)
Subtitle of host publicationproceedings of the 14th european conference
Place of PublicationNew York
PublisherIEEE
Pages1-10
Number of pages10
ISBN (Print)9781612841670
Publication statusPublished - 1 Sep 2011
Event2011 14th European Conference on Power Electronics and Applications, EPE 2011 - Birmingham, United Kingdom
Duration: 30 Aug 20111 Sep 2011

Conference

Conference2011 14th European Conference on Power Electronics and Applications, EPE 2011
Abbreviated titleEPE 2011
CountryUnited Kingdom
CityBirmingham
Period30/08/111/09/11

Keywords

  • propulsion
  • real time systems
  • software
  • hardware in the loop
  • transient analysis
  • commutation
  • hardware
  • stators

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    Loddick, S., Mupambireyi, U., Blair, S., Booth, C., Li, X., Roscoe, A. J., Daffey, K., & Rn, L. J. W. (2011). The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms. In Power electronics and applications (EPE 2011): proceedings of the 14th european conference (pp. 1-10). IEEE.