The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

S. Loddick; U. Mupambireyi; S. Blair; C. Booth; X. Li; Andrew J. Roscoe; K. Daffey; L.J.W. Rn

The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

S. Loddick, U. Mupambireyi, S. Blair, C. Booth, X. Li, Andrew J. Roscoe, K. Daffey, L.J.W. Rn

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

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Abstract

Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs).

Original language	English
Title of host publication	Power electronics and applications (EPE 2011)
Subtitle of host publication	proceedings of the 14th european conference
Place of Publication	New York
Publisher	IEEE
Pages	1-10
Number of pages	10
ISBN (Print)	9781612841670
Publication status	Published - 1 Sept 2011
Event	2011 14th European Conference on Power Electronics and Applications, EPE 2011 - Birmingham, United Kingdom Duration: 30 Aug 2011 → 1 Sept 2011

Conference

Conference	2011 14th European Conference on Power Electronics and Applications, EPE 2011
Abbreviated title	EPE 2011
Country/Territory	United Kingdom
City	Birmingham
Period	30/08/11 → 1/09/11

Keywords

propulsion
real time systems
software
hardware in the loop
transient analysis
commutation
hardware
stators

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C_2011_Loddick_EPE_Converteam_RTDS_PostPrintAccepted author manuscript, 989 KB

Cite this

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title = "The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms",

abstract = "Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs). ",

keywords = "propulsion, real time systems, software, hardware in the loop, transient analysis, commutation, hardware, stators",

author = "S. Loddick and U. Mupambireyi and S. Blair and C. Booth and X. Li and Roscoe, {Andrew J.} and K. Daffey and L.J.W. Rn",

year = "2011",

month = sep,

day = "1",

language = "English",

isbn = "9781612841670",

pages = "1--10",

booktitle = "Power electronics and applications (EPE 2011)",

publisher = "IEEE",

note = "2011 14th European Conference on Power Electronics and Applications, EPE 2011, EPE 2011 ; Conference date: 30-08-2011 Through 01-09-2011",

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Loddick, S, Mupambireyi, U, Blair, S, Booth, C, Li, X, Roscoe, AJ, Daffey, K & Rn, LJW 2011, The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms. in Power electronics and applications (EPE 2011): proceedings of the 14th european conference . IEEE, New York, pp. 1-10, 2011 14th European Conference on Power Electronics and Applications, EPE 2011, Birmingham, United Kingdom, 30/08/11.

TY - GEN

T1 - The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

AU - Loddick, S.

AU - Mupambireyi, U.

AU - Blair, S.

AU - Booth, C.

AU - Li, X.

AU - Roscoe, Andrew J.

AU - Daffey, K.

AU - Rn, L.J.W.

PY - 2011/9/1

Y1 - 2011/9/1

N2 - Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs).

AB - Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs).

KW - propulsion

KW - real time systems

KW - software

KW - hardware in the loop

KW - transient analysis

KW - commutation

KW - hardware

KW - stators

UR - http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=6020339&queryText%3Dreal+time+digital+simulation+and+hardware%26openedRefinements%3D*%26filter%3DAND%28NOT%284283010803%29%29%26searchField%3DSearch+All

M3 - Conference contribution book

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BT - Power electronics and applications (EPE 2011)

PB - IEEE

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T2 - 2011 14th European Conference on Power Electronics and Applications, EPE 2011

Y2 - 30 August 2011 through 1 September 2011

ER -

The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

Abstract

Conference

Keywords

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Dynamic Power Systems Laboratory

Cite this

The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Equipment

Dynamic Power Systems Laboratory

Cite this