Low power demonstrators are commonly used to validate novel control algorithms. However, the response of the demonstrator to network transients and faults is often unexplored. The importance of this work has, in the past, justified facilities such as the T45 Shore Integration Test Facility (SITF) at the Electric Ship Technology Demonstrator (ESTD). This paper presents the use of real time digital simulation and hardware in the loop to de-risk a innovative control algorithm with respect to network transients and faults. A novel feature of the study is the modelling of events at the power electronics level (time steps of circa 2 μs) and the system level (time steps of circa 50 μs).
|Title of host publication||Power electronics and applications (EPE 2011)|
|Subtitle of host publication||proceedings of the 14th european conference|
|Place of Publication||New York|
|Number of pages||10|
|Publication status||Published - 1 Sep 2011|
|Event||2011 14th European Conference on Power Electronics and Applications, EPE 2011 - Birmingham, United Kingdom|
Duration: 30 Aug 2011 → 1 Sep 2011
|Conference||2011 14th European Conference on Power Electronics and Applications, EPE 2011|
|Abbreviated title||EPE 2011|
|Period||30/08/11 → 1/09/11|
- real time systems
- hardware in the loop
- transient analysis
Loddick, S., Mupambireyi, U., Blair, S., Booth, C., Li, X., Roscoe, A. J., Daffey, K., & Rn, L. J. W. (2011). The use of real time digital simulation and hardware in the loop to de-risk novel control algorithms. In Power electronics and applications (EPE 2011): proceedings of the 14th european conference (pp. 1-10). IEEE.