The effect of pipelining feedback loops in high speed DSP systems

S.W. Alexander, R.W. Stewart

Research output: Contribution to conferencePaper

Abstract

Many of today’s Electronic Design Automation (EDA) tools include Intellectual Property (IP) cores that are fully pipelined to increase data throughput. Using these cores to implement data paths that do not involve feedback can result in fast, efficient designs. However, if they are used within a feedback loop this is not always the case. This paper examines the effects that using pipelined cores in
feedback loops can have on a design. By considering two designs that implement a Givens rotation using feedback, which is used in QR decomposition [1], it is shown that, even though a pipelined design can be clocked faster, its data throughput is less than a non-pipelined design. Also, the non-pipelined design is shown to be smaller and consumes less power. Finally, a suggestion for a more
efficient use of pipelining in feedback loops is presented, based on channel interleaving [2].
LanguageEnglish
PagesV145- V148
Number of pages4
DOIs
Publication statusPublished - 9 May 2005

Fingerprint

Feedback
Throughput
Decomposition

Keywords

  • pipelining
  • feedback loops
  • DSP systems

Cite this

@conference{c48ebbb7f805400389845c5766e2fcd2,
title = "The effect of pipelining feedback loops in high speed DSP systems",
abstract = "Many of today’s Electronic Design Automation (EDA) tools include Intellectual Property (IP) cores that are fully pipelined to increase data throughput. Using these cores to implement data paths that do not involve feedback can result in fast, efficient designs. However, if they are used within a feedback loop this is not always the case. This paper examines the effects that using pipelined cores infeedback loops can have on a design. By considering two designs that implement a Givens rotation using feedback, which is used in QR decomposition [1], it is shown that, even though a pipelined design can be clocked faster, its data throughput is less than a non-pipelined design. Also, the non-pipelined design is shown to be smaller and consumes less power. Finally, a suggestion for a moreefficient use of pipelining in feedback loops is presented, based on channel interleaving [2].",
keywords = "pipelining, feedback loops, DSP systems",
author = "S.W. Alexander and R.W. Stewart",
note = "This paper appears in: Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on ISSN: 1520-6149 ; Print ISBN: 0-7803-8874-7",
year = "2005",
month = "5",
day = "9",
doi = "10.1109/ICASSP.2005.1416261",
language = "English",
pages = "V145-- V148",

}

The effect of pipelining feedback loops in high speed DSP systems. / Alexander, S.W.; Stewart, R.W.

2005. V145- V148.

Research output: Contribution to conferencePaper

TY - CONF

T1 - The effect of pipelining feedback loops in high speed DSP systems

AU - Alexander, S.W.

AU - Stewart, R.W.

N1 - This paper appears in: Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on ISSN: 1520-6149 ; Print ISBN: 0-7803-8874-7

PY - 2005/5/9

Y1 - 2005/5/9

N2 - Many of today’s Electronic Design Automation (EDA) tools include Intellectual Property (IP) cores that are fully pipelined to increase data throughput. Using these cores to implement data paths that do not involve feedback can result in fast, efficient designs. However, if they are used within a feedback loop this is not always the case. This paper examines the effects that using pipelined cores infeedback loops can have on a design. By considering two designs that implement a Givens rotation using feedback, which is used in QR decomposition [1], it is shown that, even though a pipelined design can be clocked faster, its data throughput is less than a non-pipelined design. Also, the non-pipelined design is shown to be smaller and consumes less power. Finally, a suggestion for a moreefficient use of pipelining in feedback loops is presented, based on channel interleaving [2].

AB - Many of today’s Electronic Design Automation (EDA) tools include Intellectual Property (IP) cores that are fully pipelined to increase data throughput. Using these cores to implement data paths that do not involve feedback can result in fast, efficient designs. However, if they are used within a feedback loop this is not always the case. This paper examines the effects that using pipelined cores infeedback loops can have on a design. By considering two designs that implement a Givens rotation using feedback, which is used in QR decomposition [1], it is shown that, even though a pipelined design can be clocked faster, its data throughput is less than a non-pipelined design. Also, the non-pipelined design is shown to be smaller and consumes less power. Finally, a suggestion for a moreefficient use of pipelining in feedback loops is presented, based on channel interleaving [2].

KW - pipelining

KW - feedback loops

KW - DSP systems

UR - http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01416261

U2 - 10.1109/ICASSP.2005.1416261

DO - 10.1109/ICASSP.2005.1416261

M3 - Paper

SP - V145- V148

ER -