Concurrent processing techniques are applied to real-time high-performance control problems. In particular, four shortest-latency systolic array architectures are developed for controller implementation in such problems at word level. A technique termed 'M-expanded pipelining' is used to pipeline these architectures to an arbitrary deeper level. Some preliminary results concerning the expected performance of these architectures are presented.
|Number of pages||2|
|Journal||Proceedings of the IEEE Conference on Decision and Control|
|Publication status||Published - 1 Dec 1988|
- systolic array
- concurrent processing
- real-time high performance control