Systolic array based concurrent processing for real-time high performance control

E. Rogers; Yun Li

Systolic array based concurrent processing for real-time high performance control

E. Rogers^*, Yun Li

^*Corresponding author for this work

Faculty Of Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

Concurrent processing techniques are applied to real-time high-performance control problems. In particular, four shortest-latency systolic array architectures are developed for controller implementation in such problems at word level. A technique termed 'M-expanded pipelining' is used to pipeline these architectures to an arbitrary deeper level. Some preliminary results concerning the expected performance of these architectures are presented.

Original language	English
Pages (from-to)	2236-2237
Number of pages	2
Journal	Proceedings of the IEEE Conference on Decision and Control
Publication status	Published - 1 Dec 1988

Keywords

systolic array
concurrent processing
real-time high performance control

Cite this

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title = "Systolic array based concurrent processing for real-time high performance control",

abstract = "Concurrent processing techniques are applied to real-time high-performance control problems. In particular, four shortest-latency systolic array architectures are developed for controller implementation in such problems at word level. A technique termed 'M-expanded pipelining' is used to pipeline these architectures to an arbitrary deeper level. Some preliminary results concerning the expected performance of these architectures are presented.",

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author = "E. Rogers and Yun Li",

year = "1988",

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AB - Concurrent processing techniques are applied to real-time high-performance control problems. In particular, four shortest-latency systolic array architectures are developed for controller implementation in such problems at word level. A technique termed 'M-expanded pipelining' is used to pipeline these architectures to an arbitrary deeper level. Some preliminary results concerning the expected performance of these architectures are presented.

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KW - concurrent processing

KW - real-time high performance control

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JO - Proceedings of the IEEE Conference on Decision and Control

JF - Proceedings of the IEEE Conference on Decision and Control

ER -

Systolic array based concurrent processing for real-time high performance control

Abstract

Keywords

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