Sampled-data supervisory control

Ryan J. Leduc, Yu Wang, Fahim Ahmed

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors, and the concurrency and timing delay issues involved. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller. We present controllability and non-blocking results for SD controllers.
Original languageEnglish
Pages (from-to)541-579
Number of pages39
JournalDiscrete Event Dynamic Systems
Volume24
Issue number4
Early online date8 Nov 2013
DOIs
Publication statusPublished - 31 Dec 2014

Fingerprint

Sampled-data Control
Supervisory Control
Discrete Event Systems
Discrete event simulation
Controllability
Controller
Controllers
Supervisory personnel
Concurrency
Clocks
Output
Timing
Update
Sufficient
Series

Keywords

  • timed discrete-event systems
  • supervisory control
  • sampled-data controller
  • Moore finite state machine

Cite this

Leduc, Ryan J. ; Wang, Yu ; Ahmed, Fahim. / Sampled-data supervisory control. In: Discrete Event Dynamic Systems . 2014 ; Vol. 24, No. 4. pp. 541-579.
@article{e11222d321444db48a5ca3426ea351f1,
title = "Sampled-data supervisory control",
abstract = "This paper focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors, and the concurrency and timing delay issues involved. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller. We present controllability and non-blocking results for SD controllers.",
keywords = "timed discrete-event systems, supervisory control , sampled-data controller, Moore finite state machine",
author = "Leduc, {Ryan J.} and Yu Wang and Fahim Ahmed",
year = "2014",
month = "12",
day = "31",
doi = "10.1007/s10626-013-0172-4",
language = "English",
volume = "24",
pages = "541--579",
journal = "Discrete Event Dynamic Systems",
issn = "0924-6703",
number = "4",

}

Sampled-data supervisory control. / Leduc, Ryan J.; Wang, Yu; Ahmed, Fahim.

In: Discrete Event Dynamic Systems , Vol. 24, No. 4, 31.12.2014, p. 541-579.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Sampled-data supervisory control

AU - Leduc, Ryan J.

AU - Wang, Yu

AU - Ahmed, Fahim

PY - 2014/12/31

Y1 - 2014/12/31

N2 - This paper focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors, and the concurrency and timing delay issues involved. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller. We present controllability and non-blocking results for SD controllers.

AB - This paper focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors, and the concurrency and timing delay issues involved. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller. We present controllability and non-blocking results for SD controllers.

KW - timed discrete-event systems

KW - supervisory control

KW - sampled-data controller

KW - Moore finite state machine

U2 - 10.1007/s10626-013-0172-4

DO - 10.1007/s10626-013-0172-4

M3 - Article

VL - 24

SP - 541

EP - 579

JO - Discrete Event Dynamic Systems

JF - Discrete Event Dynamic Systems

SN - 0924-6703

IS - 4

ER -