Sampled-data supervisory control

Ryan J. Leduc, Yu Wang, Fahim Ahmed

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors, and the concurrency and timing delay issues involved. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller. We present controllability and non-blocking results for SD controllers.
Original languageEnglish
Pages (from-to)541-579
Number of pages39
JournalDiscrete Event Dynamic Systems
Volume24
Issue number4
Early online date8 Nov 2013
DOIs
Publication statusPublished - 31 Dec 2014

Keywords

  • timed discrete-event systems
  • supervisory control
  • sampled-data controller
  • Moore finite state machine

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