Systolic/wavefront array architectures for real-time digital control system design are considered. Described is the development of word-level systolic and wavefront architectures for recursive filtering and on-line feedback control schemes. Each of these arrays uses only one type of cell and has the same array configuration. These offer a word-level shortest processing delay (or system latency) of one cycle, while retaining a very high throughput rate, and hence are applicable to real-time feedback control engineering problems.
|Number of pages||3|
|Journal||Proceedings of the IEEE Conference on Decision and Control|
|Publication status||Published - 5 Dec 1990|
- control system CAD
- digital control
- systolic arrays