Quasi two-level operation of a five-level inverter

G.P. Adam; S.J. Finney; B.W. Williams

doi:10.1109/CPE.2007.4296557

Quasi two-level operation of a five-level inverter

G.P. Adam, S.J. Finney, B.W. Williams

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

5 Citations (Scopus)

Abstract

In this paper a five-level inverter operational mode termed quasi two-level operation is proposed. The multilevel capacitors function in a soft clamping mode where capacitor voltage balancing is maintained by varying the transient dwell time at each level. Two balancing techniques are proposed. The first is based on the selection of suitable resistors to be connected across each dc link capacitor in order to maintain balance. The second method is based on varying the dwell time at the intermediate nodes of the dc link capacitors. The validity of the operational mode and the two proposed balancing techniques are confirmed by simulations and experiments.

Original language	English
Title of host publication	Proceedings of Compatibility in Power Electronics, 2007
Publisher	IEEE
Pages	1-6
Number of pages	6
ISBN (Print)	1-4244-1055-X
DOIs	https://doi.org/10.1109/CPE.2007.4296557
Publication status	Published - 4 Sept 2007
Event	5th International IEEE Conference on Compatibility in Power Electronics - Gdańsk, Poland Duration: 29 May 2007 → 1 Jun 2007 http://www.pedc.am.gdynia.pl/cpe2007/

Conference

Conference	5th International IEEE Conference on Compatibility in Power Electronics
Abbreviated title	CPE2007
Country/Territory	Poland
City	Gdańsk
Period	29/05/07 → 1/06/07
Internet address	http://www.pedc.am.gdynia.pl/cpe2007/

Keywords

capacitors
circuits
clamps
diodes
pulse width modulation inverters
resistors

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10.1109/CPE.2007.4296557

Cite this

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title = "Quasi two-level operation of a five-level inverter",

abstract = "In this paper a five-level inverter operational mode termed quasi two-level operation is proposed. The multilevel capacitors function in a soft clamping mode where capacitor voltage balancing is maintained by varying the transient dwell time at each level. Two balancing techniques are proposed. The first is based on the selection of suitable resistors to be connected across each dc link capacitor in order to maintain balance. The second method is based on varying the dwell time at the intermediate nodes of the dc link capacitors. The validity of the operational mode and the two proposed balancing techniques are confirmed by simulations and experiments.",

keywords = "capacitors, circuits, clamps, diodes, pulse width modulation inverters , resistors",

author = "G.P. Adam and S.J. Finney and B.W. Williams",

year = "2007",

month = sep,

day = "4",

doi = "10.1109/CPE.2007.4296557",

language = "English",

isbn = "1-4244-1055-X",

pages = "1--6",

booktitle = "Proceedings of Compatibility in Power Electronics, 2007",

publisher = "IEEE",

note = "5th International IEEE Conference on Compatibility in Power Electronics, CPE2007 ; Conference date: 29-05-2007 Through 01-06-2007",

url = "http://www.pedc.am.gdynia.pl/cpe2007/",

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TY - GEN

T1 - Quasi two-level operation of a five-level inverter

AU - Adam, G.P.

AU - Finney, S.J.

AU - Williams, B.W.

PY - 2007/9/4

Y1 - 2007/9/4

N2 - In this paper a five-level inverter operational mode termed quasi two-level operation is proposed. The multilevel capacitors function in a soft clamping mode where capacitor voltage balancing is maintained by varying the transient dwell time at each level. Two balancing techniques are proposed. The first is based on the selection of suitable resistors to be connected across each dc link capacitor in order to maintain balance. The second method is based on varying the dwell time at the intermediate nodes of the dc link capacitors. The validity of the operational mode and the two proposed balancing techniques are confirmed by simulations and experiments.

AB - In this paper a five-level inverter operational mode termed quasi two-level operation is proposed. The multilevel capacitors function in a soft clamping mode where capacitor voltage balancing is maintained by varying the transient dwell time at each level. Two balancing techniques are proposed. The first is based on the selection of suitable resistors to be connected across each dc link capacitor in order to maintain balance. The second method is based on varying the dwell time at the intermediate nodes of the dc link capacitors. The validity of the operational mode and the two proposed balancing techniques are confirmed by simulations and experiments.

KW - capacitors

KW - circuits

KW - clamps

KW - diodes

KW - pulse width modulation inverters

KW - resistors

U2 - 10.1109/CPE.2007.4296557

DO - 10.1109/CPE.2007.4296557

M3 - Conference contribution book

SN - 1-4244-1055-X

SP - 1

EP - 6

BT - Proceedings of Compatibility in Power Electronics, 2007

PB - IEEE

T2 - 5th International IEEE Conference on Compatibility in Power Electronics

Y2 - 29 May 2007 through 1 June 2007

ER -

Quasi two-level operation of a five-level inverter

Abstract

Conference

Keywords

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