Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems

Frederick Page; Stephen Finney; Derrick Holliday; Lie Xu; Barry Williams

Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems

Frederick Page, Stephen Finney, Derrick Holliday, Lie Xu, Barry Williams

Electronic And Electrical Engineering

Research output: Contribution to conference › Paper

212 Downloads (Pure)

Abstract

HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system

Original language	English
Publication status	Published - 28 May 2015
Event	Cigré International Symposium : Across Borders - HVDC Systems and Market Integration - Lund, Sweden Duration: 27 May 2015 → 28 May 2015

Conference

Conference	Cigré International Symposium : Across Borders - HVDC Systems and Market Integration
Country	Sweden
City	Lund
Period	27/05/15 → 28/05/15

Keywords

HVDC systems
circuit breaker

Access to Document

Page-etal-Cigre-2015-Optimisation-of-passive-system-components-to-minimise-DC-circuit-breakerAccepted author manuscript, 1.14 MB

http://b4.cigre.org/Events/Cigre-events/2015-Cigre-Symposium-in-Lund-Sweden

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@conference{38901f8705674addba502c9bb57e842a,

title = "Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems",

abstract = "HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system",

keywords = "HVDC systems, circuit breaker",

author = "Frederick Page and Stephen Finney and Derrick Holliday and Lie Xu and Barry Williams",

year = "2015",

month = may,

day = "28",

language = "English",

note = "Cigr{\'e} International Symposium : Across Borders - HVDC Systems and Market Integration ; Conference date: 27-05-2015 Through 28-05-2015",

}

Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems. / Page, Frederick; Finney, Stephen; Holliday, Derrick ; Xu, Lie ; Williams, Barry.

2015. Paper presented at Cigré International Symposium : Across Borders - HVDC Systems and Market Integration, Lund, Sweden.

Research output: Contribution to conference › Paper

TY - CONF

T1 - Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems

AU - Page, Frederick

AU - Finney, Stephen

AU - Holliday, Derrick

AU - Xu, Lie

AU - Williams, Barry

PY - 2015/5/28

Y1 - 2015/5/28

N2 - HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system

AB - HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system

KW - HVDC systems

KW - circuit breaker

UR - http://b4.cigre.org/Events/Cigre-events/2015-Cigre-Symposium-in-Lund-Sweden

M3 - Paper

T2 - Cigré International Symposium : Across Borders - HVDC Systems and Market Integration

Y2 - 27 May 2015 through 28 May 2015

ER -