Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems

Frederick Page, Stephen Finney, Derrick Holliday, Lie Xu, Barry Williams

Research output: Contribution to conferencePaper

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Abstract

HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system
Original languageEnglish
Publication statusPublished - 28 May 2015
EventCigré International Symposium : Across Borders - HVDC Systems and Market Integration - Lund, Sweden
Duration: 27 May 201528 May 2015

Conference

ConferenceCigré International Symposium : Across Borders - HVDC Systems and Market Integration
CountrySweden
CityLund
Period27/05/1528/05/15

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Electric circuit breakers
Electric fault currents
Electric network analysis
Inductance
Energy dissipation

Keywords

  • HVDC systems
  • circuit breaker

Cite this

Page, F., Finney, S., Holliday, D., Xu, L., & Williams, B. (2015). Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems. Paper presented at Cigré International Symposium : Across Borders - HVDC Systems and Market Integration, Lund, Sweden.
Page, Frederick ; Finney, Stephen ; Holliday, Derrick ; Xu, Lie ; Williams, Barry. / Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems. Paper presented at Cigré International Symposium : Across Borders - HVDC Systems and Market Integration, Lund, Sweden.
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abstract = "HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system",
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Page, F, Finney, S, Holliday, D, Xu, L & Williams, B 2015, 'Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems' Paper presented at Cigré International Symposium : Across Borders - HVDC Systems and Market Integration, Lund, Sweden, 27/05/15 - 28/05/15, .

Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems. / Page, Frederick; Finney, Stephen; Holliday, Derrick; Xu, Lie; Williams, Barry.

2015. Paper presented at Cigré International Symposium : Across Borders - HVDC Systems and Market Integration, Lund, Sweden.

Research output: Contribution to conferencePaper

TY - CONF

T1 - Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems

AU - Page, Frederick

AU - Finney, Stephen

AU - Holliday, Derrick

AU - Xu, Lie

AU - Williams, Barry

PY - 2015/5/28

Y1 - 2015/5/28

N2 - HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system

AB - HVDC circuit breaker designs have commonly included additional series inductance to reduce the rate of rise of current during the initial transient period after a fault occurs, minimising the peak current stress that the circuit breaker must endure. A method of approximating the peak fault current and energy dissipation in a circuit breaker is developed, through circuit analysis of a multi-level converter (MMC) under fault conditions. These approximations are validated against simulation results for an 800kV MMC system

KW - HVDC systems

KW - circuit breaker

UR - http://b4.cigre.org/Events/Cigre-events/2015-Cigre-Symposium-in-Lund-Sweden

M3 - Paper

ER -

Page F, Finney S, Holliday D, Xu L, Williams B. Optimisation of passive system components to minimise DC circuit breaker stresses in multi-terminal HVDC systems. 2015. Paper presented at Cigré International Symposium : Across Borders - HVDC Systems and Market Integration, Lund, Sweden.