## Abstract

When FIR filters are designed floating point arithmetic is generally used. However when implemented on hardware such as ASICs, fixed point arithmetic must be used to minimise cost and power requirements. Research to minimise hardware costs has mainly focused on the quantization effects of fixed point wordlengths for the coefficients, multipliers and adders of FIR filters, but with the actual data delays assigned a uniform wordlength and essentially not optimised. This paper proposes that the wordlengths of the delay line can be non-uniform with a minimal increase in quantization noise for parallel implementation of FIR filters

where there are differences in the magnitudes of the coefficients. A non-uniform delay line allows hardware savings in terms of delay register wordlengths, delay signal wordlengths and multiplier wordlengths. Results for an FIR design are presented which demonstrate the hardware savingswhen using a non-uniform wordlength delay line

where there are differences in the magnitudes of the coefficients. A non-uniform delay line allows hardware savings in terms of delay register wordlengths, delay signal wordlengths and multiplier wordlengths. Results for an FIR design are presented which demonstrate the hardware savingswhen using a non-uniform wordlength delay line

Original language | English |
---|---|

Pages | 1003 |

Number of pages | 1006 |

Publication status | Published - Aug 2009 |

Event | 17th European Signal Processing Conference - Glasgow, Scotland Duration: 24 Aug 2009 → 28 Aug 2009 |

### Conference

Conference | 17th European Signal Processing Conference |
---|---|

City | Glasgow, Scotland |

Period | 24/08/09 → 28/08/09 |

## Keywords

- FIR filters
- FFC algorithm
- floating point to fixed point conversion
- FFC
- algorithm
- dsp system