TY - JOUR
T1 - Multichannel time-to-digital converters with automatic calibration in Xilinx Zynq-7000 FPGA devices
AU - Wang, Yu
AU - Xie, Wujun
AU - Chen, Haochang
AU - Li, David Day-Uei
N1 - © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
PY - 2021/9/15
Y1 - 2021/9/15
N2 - This paper proposes a weighted histogram method and an automatic calibration architecture to implement high-linearity time-to-digital converters (TDCs) 16 in low-cost advanced RISC machine (ARM)-based field-programmable gate arrays (FPGAs). The proposed method significantly reduces nonlinearity induced by nonuniform bins. It offers automatic calibration without manual interventions using ARM processors. Besides, our design is cost-effective in hardware consumption. We implemented and evaluated a 32-channel TDC system in a low-cost Zynq-7000 ARM-based FPGA, in which the programable logic is equivalent to a 28 nm Artix-7 FPGA. The proposed TDC offers a resolution of 9.83 ps (LSB = 9.83 ps) with good uniformity, achieving an averaged peak-peak differential nonlinearity (DNLpk-pk) of 0.27 LSB, and an averaged peak-to-peak integral nonlinearity 28 (INLpk-pk) of 0.67LSB.
AB - This paper proposes a weighted histogram method and an automatic calibration architecture to implement high-linearity time-to-digital converters (TDCs) 16 in low-cost advanced RISC machine (ARM)-based field-programmable gate arrays (FPGAs). The proposed method significantly reduces nonlinearity induced by nonuniform bins. It offers automatic calibration without manual interventions using ARM processors. Besides, our design is cost-effective in hardware consumption. We implemented and evaluated a 32-channel TDC system in a low-cost Zynq-7000 ARM-based FPGA, in which the programable logic is equivalent to a 28 nm Artix-7 FPGA. The proposed TDC offers a resolution of 9.83 ps (LSB = 9.83 ps) with good uniformity, achieving an averaged peak-peak differential nonlinearity (DNLpk-pk) of 0.27 LSB, and an averaged peak-to-peak integral nonlinearity 28 (INLpk-pk) of 0.67LSB.
KW - time-to-digital converter (TDC)
KW - carry chains
KW - field programmable gate array
UR - https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41
U2 - 10.1109/TIE.2021.3111563
DO - 10.1109/TIE.2021.3111563
M3 - Article
JO - IEEE Transactions on Industrial Electronics
JF - IEEE Transactions on Industrial Electronics
SN - 0278-0046
ER -