Multi-channel, low nonlinearity time-to-digital converters based on 20nm and 28nm FPGAs

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Abstract

Abstract—This paper presents low nonlinearity, compact and multi-channel time-to-digital converters (TDC) in Xilinx 28nm Virtex 7 and 20nm UltraScale FPGAs. The proposed TDCs integrate several innovative methods that we have developed: 1) the sub-tapped delay line (TDL) averaging topology, 2) tap timing tests, 3) a direct compensation architecture and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25 % of the logic resources. The achieved least significant bit (LSB) is 10.5ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.
Original languageEnglish
Number of pages9
JournalIEEE Transactions on Industrial Electronics
Early online date20 Jun 2018
DOIs
Publication statusPublished - 30 Nov 2018

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Field programmable gate arrays (FPGA)
Calibration
Electric delay lines
Topology
Costs

Keywords

  • carry chains
  • field-programmable gate arrays (FPGA)
  • time-of-flight
  • time-to-digital converters (TDC)
  • FPGAbased TDCs
  • multichannel TDCs

Cite this

@article{1027ea43a08941b389ec04f8e0b83574,
title = "Multi-channel, low nonlinearity time-to-digital converters based on 20nm and 28nm FPGAs",
abstract = "Abstract—This paper presents low nonlinearity, compact and multi-channel time-to-digital converters (TDC) in Xilinx 28nm Virtex 7 and 20nm UltraScale FPGAs. The proposed TDCs integrate several innovative methods that we have developed: 1) the sub-tapped delay line (TDL) averaging topology, 2) tap timing tests, 3) a direct compensation architecture and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25 {\%} of the logic resources. The achieved least significant bit (LSB) is 10.5ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.",
keywords = "carry chains, field-programmable gate arrays (FPGA), time-of-flight, time-to-digital converters (TDC), FPGAbased TDCs, multichannel TDCs",
author = "Haochang Chen and Li, {David Day-Uei}",
year = "2018",
month = "11",
day = "30",
doi = "10.1109/TIE.2018.2842787",
language = "English",
journal = "IEEE Transactions on Industrial Electronics",
issn = "0278-0046",

}

TY - JOUR

T1 - Multi-channel, low nonlinearity time-to-digital converters based on 20nm and 28nm FPGAs

AU - Chen, Haochang

AU - Li, David Day-Uei

PY - 2018/11/30

Y1 - 2018/11/30

N2 - Abstract—This paper presents low nonlinearity, compact and multi-channel time-to-digital converters (TDC) in Xilinx 28nm Virtex 7 and 20nm UltraScale FPGAs. The proposed TDCs integrate several innovative methods that we have developed: 1) the sub-tapped delay line (TDL) averaging topology, 2) tap timing tests, 3) a direct compensation architecture and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25 % of the logic resources. The achieved least significant bit (LSB) is 10.5ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.

AB - Abstract—This paper presents low nonlinearity, compact and multi-channel time-to-digital converters (TDC) in Xilinx 28nm Virtex 7 and 20nm UltraScale FPGAs. The proposed TDCs integrate several innovative methods that we have developed: 1) the sub-tapped delay line (TDL) averaging topology, 2) tap timing tests, 3) a direct compensation architecture and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25 % of the logic resources. The achieved least significant bit (LSB) is 10.5ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [-0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [-0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [-0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [-0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.

KW - carry chains

KW - field-programmable gate arrays (FPGA)

KW - time-of-flight

KW - time-to-digital converters (TDC)

KW - FPGAbased TDCs

KW - multichannel TDCs

UR - https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=41

U2 - 10.1109/TIE.2018.2842787

DO - 10.1109/TIE.2018.2842787

M3 - Article

JO - IEEE Transactions on Industrial Electronics

JF - IEEE Transactions on Industrial Electronics

SN - 0278-0046

ER -