Abstract
This paper proposes a new calibration method, the mixed-binning method, to pursue a TDC with high linearity in field-programmable gate arrays (FPGAs). This method can reduce the nonlinearity caused by large clock skews in FPGAs efficiently. Therefore, a wide dynamic range tapped delay line (TDL) TDC has been developed with maintained linearity. We evaluated this method in Xilinx 20nm UltraScale FPGAs and Xilinx 28nm Virtex-7 FPGAs. Results conduct that this method is perfectly suitable for driverless vehicle applications which require high linearity with an acceptable resolution. The proposed method also has great potentials for multi-channel applications, due to the low logic resource consumption. For a quick proof-of-concept demonstration, an 8-channel solution has also been implemented. It can be further extended to a 64-channel version soon.
Original language | English |
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Title of host publication | 2020 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP) |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Number of pages | 4 |
ISBN (Print) | 9781728195810 |
DOIs | |
Publication status | Published - 25 Dec 2020 |
Event | 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP) - Duration: 23 Sept 2020 → 25 Sept 2020 https://ebccsp2020.org/program/ |
Conference
Conference | 6th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP) |
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Period | 23/09/20 → 25/09/20 |
Internet address |
Keywords
- carry chains
- field-programmable gate array (FPGA)
- time of flight
- time-to-digital converter (TDC)
- automatic vehicle