With standard inverted-staggered amorphous silicon based TFT's, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten.
- active matrix liquid crystal displays
- amorphous silicon ,
- delay effects
- delay lines
- joining processes
- power transmission lines
Zhang, Q., Shen, D., Gleskova, H., & Wagner, S. (1998). Modeling of gate line delay in very large active matrix liquid crystal displays. IEEE Transactions on Electron Devices, 45(1), 343-345. https://doi.org/10.1109/16.658856