Modeling of gate line delay in very large active matrix liquid crystal displays

Q. Zhang, D. Shen, Helena Gleskova, S. Wagner

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

With standard inverted-staggered amorphous silicon based TFT's, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten.
LanguageEnglish
Pages343-345
Number of pages3
JournalIEEE Transactions on Electron Devices
Volume45
Issue number1
DOIs
Publication statusPublished - 1998

Fingerprint

Electric delay lines
SPICE
Amorphous silicon
Liquid crystal displays
Networks (circuits)
Substrates

Keywords

  • voltage
  • active matrix liquid crystal displays
  • amorphous silicon ,
  • conductors
  • delay effects
  • delay lines
  • joining processes
  • power transmission lines

Cite this

@article{56dc0a71469c4dbdaf7cf3aa223940a6,
title = "Modeling of gate line delay in very large active matrix liquid crystal displays",
abstract = "With standard inverted-staggered amorphous silicon based TFT's, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten.",
keywords = "voltage, active matrix liquid crystal displays , amorphous silicon ,, conductors , delay effects , delay lines , joining processes , power transmission lines",
author = "Q. Zhang and D. Shen and Helena Gleskova and S. Wagner",
year = "1998",
doi = "10.1109/16.658856",
language = "English",
volume = "45",
pages = "343--345",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
number = "1",

}

Modeling of gate line delay in very large active matrix liquid crystal displays. / Zhang, Q.; Shen, D.; Gleskova, Helena; Wagner, S.

In: IEEE Transactions on Electron Devices, Vol. 45, No. 1, 1998, p. 343-345.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Modeling of gate line delay in very large active matrix liquid crystal displays

AU - Zhang, Q.

AU - Shen, D.

AU - Gleskova, Helena

AU - Wagner, S.

PY - 1998

Y1 - 1998

N2 - With standard inverted-staggered amorphous silicon based TFT's, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten.

AB - With standard inverted-staggered amorphous silicon based TFT's, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten.

KW - voltage

KW - active matrix liquid crystal displays

KW - amorphous silicon ,

KW - conductors

KW - delay effects

KW - delay lines

KW - joining processes

KW - power transmission lines

U2 - 10.1109/16.658856

DO - 10.1109/16.658856

M3 - Article

VL - 45

SP - 343

EP - 345

JO - IEEE Transactions on Electron Devices

T2 - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 1

ER -