Low hardware consumption, resolution-configurable gray code oscillator time-to- digital converters implemented in 16nm, 20nm and 28nm FPGAs

Yu Wang, Wujun Xie, Haochang Chen, David Day-Uei Li

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)
85 Downloads (Pure)

Abstract

This article presents a low-hardware consumption, resolution-configurable, automatically calibrating gray code oscillator time-to-digital converter (TDC) in Xilinx 16-nm UltraScale+, 20-nm UltraScale and 28-nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC utilizes look-up tables as delay elements and has several innovations: 1) a sampling matrix structure to improve the resolution, 2) a virtual bin calibration method (VBCM) to achieve configurable resolutions and automatic calibration, and 3) hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-to-peak differential nonlinearity (DNLpk-pk). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNLpk-pk and 34.84 ps with 0.08 LSB averaged DNLpk-pk, respectively.

Original languageEnglish
Pages (from-to)4256-4266
Number of pages11
JournalIEEE Transactions on Industrial Electronics
Volume70
Issue number4
Early online date17 May 2022
DOIs
Publication statusPublished - 1 Apr 2023

Keywords

  • gray code oscillator (GCO)
  • field programmable gate array (FPGA)
  • low hardware consumption
  • automatic calibration
  • resolution-adjustable
  • time-to-digital converter (TDC)

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