Low hardware consumption, resolution-configurable gray code oscillator time-to- digital converters implemented in 16nm, 20nm and 28nm FPGAs

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Abstract

This paper presents a low-hardware consumption, resolution-configurable, automatically calibrating gray code oscillator time-to-digital converter (GCO-TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC utilizes LUTs as delay elements and has several innovations: 1) a sampling matrix structure to improve the resolution. 2) a virtual bin calibration method (VBCM) to achieve configurable resolutions and automatic calibration. 3) hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-to-peak differential nonlinearity (DNLpk-pk). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNLpk-pk and 34.84 ps with 0.08 LSB averaged DNLpk-pk, respectively.
Original languageEnglish
JournalIEEE Transactions on Industrial Electronics
Early online date17 May 2022
DOIs
Publication statusE-pub ahead of print - 17 May 2022

Keywords

  • gray code oscillator (GCO)
  • field programmable gate array (FPGA)
  • low hardware consumption
  • automatic calibration
  • resolution-adjustable
  • time-to-digital converter (TDC)

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