Low FPGA area multiplier blocks for full parallel FIR filters

Kenneth N. Macpherson; Robert Stewart

doi:10.1109/FPT.2004.1393275

Low FPGA area multiplier blocks for full parallel FIR filters

Kenneth N. Macpherson, Robert Stewart

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

5 Citations (Scopus)

Abstract

A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.

Original language	English
Title of host publication	Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology
Publisher	IEEE
Pages	247 - 254
Number of pages	8
ISBN (Print)	0-7803-8651-5
DOIs	https://doi.org/10.1109/FPT.2004.1393275
Publication status	Published - Dec 2004
Event	2004 IEEE International Conference on Field-Programmable Technology - Brisbane, Australia Duration: 6 Dec 2004 → 8 Dec 2004

Conference

Conference	2004 IEEE International Conference on Field-Programmable Technology
Country/Territory	Australia
City	Brisbane
Period	6/12/04 → 8/12/04

Keywords

arithmetic
field programmable gate arrays
finite impulse response filter
FIR filters
distributed arithmetic technique

Access to Document

10.1109/FPT.2004.1393275

Cite this

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title = "Low FPGA area multiplier blocks for full parallel FIR filters",

abstract = "A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.",

keywords = "arithmetic, field programmable gate arrays, finite impulse response filter , FIR filters, distributed arithmetic technique",

author = "Macpherson, {Kenneth N.} and Robert Stewart",

year = "2004",

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doi = "10.1109/FPT.2004.1393275",

language = "English",

isbn = "0-7803-8651-5",

pages = "247 -- 254",

booktitle = "Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology",

publisher = "IEEE",

note = "2004 IEEE International Conference on Field-Programmable Technology ; Conference date: 06-12-2004 Through 08-12-2004",

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TY - GEN

T1 - Low FPGA area multiplier blocks for full parallel FIR filters

AU - Macpherson, Kenneth N.

AU - Stewart, Robert

PY - 2004/12

Y1 - 2004/12

N2 - A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.

AB - A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.

KW - arithmetic

KW - field programmable gate arrays

KW - finite impulse response filter

KW - FIR filters

KW - distributed arithmetic technique

U2 - 10.1109/FPT.2004.1393275

DO - 10.1109/FPT.2004.1393275

M3 - Conference contribution book

SN - 0-7803-8651-5

SP - 247

EP - 254

BT - Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology

PB - IEEE

T2 - 2004 IEEE International Conference on Field-Programmable Technology

Y2 - 6 December 2004 through 8 December 2004

ER -

Low FPGA area multiplier blocks for full parallel FIR filters

Abstract

Conference

Keywords

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