### Abstract

Language | English |
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Title of host publication | Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology |

Publisher | IEEE |

Pages | 247 - 254 |

Number of pages | 8 |

ISBN (Print) | 0-7803-8651-5 |

DOIs | |

Publication status | Published - Dec 2004 |

Event | 2004 IEEE International Conference on Field-Programmable Technology - Brisbane, Australia Duration: 6 Dec 2004 → 8 Dec 2004 |

### Conference

Conference | 2004 IEEE International Conference on Field-Programmable Technology |
---|---|

Country | Australia |

City | Brisbane |

Period | 6/12/04 → 8/12/04 |

### Fingerprint

### Keywords

- arithmetic
- field programmable gate arrays
- finite impulse response filter
- FIR filters
- distributed arithmetic technique

### Cite this

*Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology*(pp. 247 - 254). IEEE. https://doi.org/10.1109/FPT.2004.1393275

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*Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology.*IEEE, pp. 247 - 254, 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, 6/12/04. https://doi.org/10.1109/FPT.2004.1393275

**Low FPGA area multiplier blocks for full parallel FIR filters.** / Macpherson, Kenneth N.; Stewart, Robert.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

TY - GEN

T1 - Low FPGA area multiplier blocks for full parallel FIR filters

AU - Macpherson, Kenneth N.

AU - Stewart, Robert

PY - 2004/12

Y1 - 2004/12

N2 - A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.

AB - A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.

KW - arithmetic

KW - field programmable gate arrays

KW - finite impulse response filter

KW - FIR filters

KW - distributed arithmetic technique

U2 - 10.1109/FPT.2004.1393275

DO - 10.1109/FPT.2004.1393275

M3 - Conference contribution book

SN - 0-7803-8651-5

SP - 247

EP - 254

BT - Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology

PB - IEEE

ER -