Low FPGA area multiplier blocks for full parallel FIR filters

Kenneth N. Macpherson, Robert Stewart

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

4 Citations (Scopus)

Abstract

A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.
Original languageEnglish
Title of host publicationProceedings of the 2004 IEEE International Conference on Field-Programmable Technology
PublisherIEEE
Pages247 - 254
Number of pages8
ISBN (Print)0-7803-8651-5
DOIs
Publication statusPublished - Dec 2004
Event2004 IEEE International Conference on Field-Programmable Technology - Brisbane, Australia
Duration: 6 Dec 20048 Dec 2004

Conference

Conference2004 IEEE International Conference on Field-Programmable Technology
CountryAustralia
CityBrisbane
Period6/12/048/12/04

Keywords

  • arithmetic
  • field programmable gate arrays
  • finite impulse response filter
  • FIR filters
  • distributed arithmetic technique

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