Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH

Craig Ramsay; Louise H. Crockett; Robert W. Stewart

doi:10.1109/IEEECONF53345.2021.9723107

Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH

Craig Ramsay, Louise H. Crockett, Robert W. Stewart

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

1 Citation (Scopus)

225 Downloads (Pure)

Abstract

We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches in a novel hierarchy: efficient parallelism with Fast FIR Algorithm (FFA) structures, and efficient multiplierless FIR implementations with Hcub. The resource usage advantages (in both area and type) are compared with similar output from the traditional architecture, exemplified by vendor tools, as well as the Hcub-based filters without the FFA optimisation. Although these techniques are well studied individually in the literature, they have not enjoyed mainstream use as their structural complexity proves awkward to capture with traditional Hardware Description Languages (HDLs). This work continues a discussion of the use of functional programming techniques in hardware description, highlighting the benefits of having easily composable circuit generators.

Original language	English
Title of host publication	55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021
Editors	Michael B. Matthews
Place of Publication	New York, NY
Publisher	IEEE
Pages	925-932
Number of pages	8
ISBN (Electronic)	9781665458283
ISBN (Print)	9781665458290
DOIs	https://doi.org/10.1109/IEEECONF53345.2021.9723107
Publication status	Published - 4 Mar 2022
Event	55th Asilomar Conference on Signals, Systems & Computers - Asilomar Grounds, Pacific Grove, United States Duration: 31 Oct 2021 → 4 Nov 2021 Conference number: 55 https://asilomarsscconf.org/

Publication series

Name	Asilomar Conference on Signals, Systems, and Computers
Publisher	IEEE
ISSN (Print)	1058-6393
ISSN (Electronic)	2576-2303

Conference

Conference	55th Asilomar Conference on Signals, Systems & Computers
Country/Territory	United States
City	Pacific Grove
Period	31/10/21 → 4/11/21
Internet address	https://asilomarsscconf.org/

Keywords

digital signal processing
field programmable gate array
functional programming
multiplierless parallel filters

Access to Document

10.1109/IEEECONF53345.2021.9723107

Ramsay-etal-Asilomar-2021-Low-Cost-Parallel-Clash-FiltersAccepted author manuscript, 914 KBLicence: Strath_1

Cite this

@inproceedings{f52f727fde9342bea9f7e7a204db24a2,

title = "Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH",

abstract = "We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches in a novel hierarchy: efficient parallelism with Fast FIR Algorithm (FFA) structures, and efficient multiplierless FIR implementations with Hcub. The resource usage advantages (in both area and type) are compared with similar output from the traditional architecture, exemplified by vendor tools, as well as the Hcub-based filters without the FFA optimisation. Although these techniques are well studied individually in the literature, they have not enjoyed mainstream use as their structural complexity proves awkward to capture with traditional Hardware Description Languages (HDLs). This work continues a discussion of the use of functional programming techniques in hardware description, highlighting the benefits of having easily composable circuit generators.",

keywords = "digital signal processing, field programmable gate array, functional programming, multiplierless parallel filters",

author = "Craig Ramsay and Crockett, {Louise H.} and Stewart, {Robert W.}",

note = "{\textcopyright} 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.; 55th Asilomar Conference on Signals, Systems & Computers ; Conference date: 31-10-2021 Through 04-11-2021",

year = "2022",

month = mar,

day = "4",

doi = "10.1109/IEEECONF53345.2021.9723107",

language = "English",

isbn = "9781665458290",

series = "Asilomar Conference on Signals, Systems, and Computers",

publisher = "IEEE",

pages = "925--932",

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booktitle = "55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021",

url = "https://asilomarsscconf.org/",

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Ramsay, C, Crockett, LH & Stewart, RW 2022, Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH. in MB Matthews (ed.), 55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021. Asilomar Conference on Signals, Systems, and Computers, IEEE, New York, NY, pp. 925-932, 55th Asilomar Conference on Signals, Systems & Computers, Pacific Grove, California, United States, 31/10/21. https://doi.org/10.1109/IEEECONF53345.2021.9723107

Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH. / Ramsay, Craig; Crockett, Louise H.; Stewart, Robert W.
55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021. ed. / Michael B. Matthews. New York, NY: IEEE, 2022. p. 925-932 (Asilomar Conference on Signals, Systems, and Computers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

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AU - Ramsay, Craig

AU - Crockett, Louise H.

AU - Stewart, Robert W.

N1 - Conference code: 55

PY - 2022/3/4

Y1 - 2022/3/4

N2 - We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches in a novel hierarchy: efficient parallelism with Fast FIR Algorithm (FFA) structures, and efficient multiplierless FIR implementations with Hcub. The resource usage advantages (in both area and type) are compared with similar output from the traditional architecture, exemplified by vendor tools, as well as the Hcub-based filters without the FFA optimisation. Although these techniques are well studied individually in the literature, they have not enjoyed mainstream use as their structural complexity proves awkward to capture with traditional Hardware Description Languages (HDLs). This work continues a discussion of the use of functional programming techniques in hardware description, highlighting the benefits of having easily composable circuit generators.

AB - We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches in a novel hierarchy: efficient parallelism with Fast FIR Algorithm (FFA) structures, and efficient multiplierless FIR implementations with Hcub. The resource usage advantages (in both area and type) are compared with similar output from the traditional architecture, exemplified by vendor tools, as well as the Hcub-based filters without the FFA optimisation. Although these techniques are well studied individually in the literature, they have not enjoyed mainstream use as their structural complexity proves awkward to capture with traditional Hardware Description Languages (HDLs). This work continues a discussion of the use of functional programming techniques in hardware description, highlighting the benefits of having easily composable circuit generators.

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KW - field programmable gate array

KW - functional programming

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SN - 9781665458290

T3 - Asilomar Conference on Signals, Systems, and Computers

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BT - 55th Asilomar Conference on Signals, Systems and Computers, ACSSC 2021

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PB - IEEE

CY - New York, NY

T2 - 55th Asilomar Conference on Signals, Systems & Computers

Y2 - 31 October 2021 through 4 November 2021

ER -

Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH

Abstract

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Conference

Keywords

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Doctoral Training Partnership (DTP 2016-2017 University of Strathclyde) | Ramsay, Craig

Data for: "Low-cost, High-speed Parallel FIR Filters for RFSoC Front-Ends Enabled by CλaSH"

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Low-cost, high-speed parallel FIR filters for RFSoC front-ends enabled by CλaSH

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Projects

Doctoral Training Partnership (DTP 2016-2017 University of Strathclyde) | Ramsay, Craig

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Data for: "Low-cost, High-speed Parallel FIR Filters for RFSoC Front-Ends Enabled by CλaSH"

Cite this