Layout Optimization of Integrated Trench VDMOS Arrays

Terry Dyer (Inventor), Andrew Strachan (Inventor)

Research output: Patent

Abstract

An economical integration of trench VDMOS devices into a conventional BCD process is provided, with the optimization of key aspects of the device layout for low R<SUB>ds(on) </SUB>area. Specifically, trench orientation, array geometry, the number of source cells between drain pickups and drain-source spacing are independently optimized. In one embodiment of the invention, the optimized device utilizes a rectangular cell array with an elongation ratio in the range of 5/3-7/3, with a ratio of 5/3 being preferred, and a cell orientation at 45° with respect to the wafer flat on a 100 wafer.
Original languageEnglish
Patent numberUS patent 7,071,513
IPCH01L21/8249
Priority date28/05/04
Publication statusPublished - 4 Jul 2006

Keywords

  • CMOS circuits
  • DMOS circuits
  • crystalline silicon

Cite this

Dyer, T., & Strachan, A. (2006). IPC No. H01L21/8249. Layout Optimization of Integrated Trench VDMOS Arrays. (Patent No. US patent 7,071,513 ).