Abstract
An economical integration of trench VDMOS devices into a conventional BCD process is provided, with the optimization of key aspects of the device layout for low R<SUB>ds(on) </SUB>area. Specifically, trench orientation, array geometry, the number of source cells between drain pickups and drain-source spacing are independently optimized. In one embodiment of the invention, the optimized device utilizes a rectangular cell array with an elongation ratio in the range of 5/3-7/3, with a ratio of 5/3 being preferred, and a cell orientation at 45° with respect to the wafer flat on a 100 wafer.
Original language | English |
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Patent number | US patent 7,071,513 |
IPC | H01L21/8249 |
Priority date | 28/05/04 |
Publication status | Published - 4 Jul 2006 |
Keywords
- CMOS circuits
- DMOS circuits
- crystalline silicon