IP core for hardware RAID 6 acceleration

M.P. Gilroy; J. Irvine; Gideon  Riddell

IP core for hardware RAID 6 acceleration

M.P. Gilroy, J. Irvine, Gideon Riddell

Electronic And Electrical Engineering

Research output: Contribution to conference › Paper

Abstract

As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures.
In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware

Original language	English
Publication status	Published - 2006
Event	IP Based SOC Design Conference and Exhibition - Grenoble, France Duration: 6 Dec 2006 → 7 Dec 2006

Conference

Conference	IP Based SOC Design Conference and Exhibition
Abbreviated title	IP/SOC 2006
Country/Territory	France
City	Grenoble
Period	6/12/06 → 7/12/06

Keywords

IP core
hardware
RAID 6
acceleration

Cite this

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title = "IP core for hardware RAID 6 acceleration",

abstract = "As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware ",

keywords = "IP core, hardware, RAID 6, acceleration",

author = "M.P. Gilroy and J. Irvine and Gideon Riddell",

year = "2006",

language = "English",

note = "IP Based SOC Design Conference and Exhibition, IP/SOC 2006 ; Conference date: 06-12-2006 Through 07-12-2006",

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TY - CONF

T1 - IP core for hardware RAID 6 acceleration

AU - Gilroy, M.P.

AU - Irvine, J.

AU - Riddell, Gideon

PY - 2006

Y1 - 2006

N2 - As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware

AB - As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware

KW - IP core

KW - hardware

KW - RAID 6

KW - acceleration

UR - http://www.design-reuse.com/articles/16457/ip-core-for-raid-6-hardware-acceleration.html

M3 - Paper

T2 - IP Based SOC Design Conference and Exhibition

Y2 - 6 December 2006 through 7 December 2006

ER -

IP core for hardware RAID 6 acceleration

Abstract

Conference

Keywords

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