IP core for hardware RAID 6 acceleration

M.P. Gilroy, J. Irvine, Gideon Riddell

Research output: Contribution to conference › Paper

Abstract

As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures.
In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware
Original languageEnglish
Publication statusPublished - 2006
EventIP Based SOC Design Conference and Exhibition - Grenoble, France
Duration: 6 Dec 2006 → 7 Dec 2006

Conference

ConferenceIP Based SOC Design Conference and Exhibition
Abbreviated titleIP/SOC 2006
CountryFrance
CityGrenoble
Period6/12/06 → 7/12/06

Fingerprint

Hardware
Computer hardware description languages
Particle accelerators
Field programmable gate arrays (FPGA)
Intellectual property core

Keywords

  • IP core
  • hardware
  • RAID 6
  • acceleration

Cite this

Gilroy, M. P., Irvine, J., & Riddell, G. (2006). IP core for hardware RAID 6 acceleration. Paper presented at IP Based SOC Design Conference and Exhibition, Grenoble, France.
Gilroy, M.P. ; Irvine, J. ; Riddell, Gideon . / IP core for hardware RAID 6 acceleration. Paper presented at IP Based SOC Design Conference and Exhibition, Grenoble, France.
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Gilroy, MP, Irvine, J & Riddell, G 2006, 'IP core for hardware RAID 6 acceleration' Paper presented at IP Based SOC Design Conference and Exhibition, Grenoble, France, 6/12/06 - 7/12/06, .

IP core for hardware RAID 6 acceleration. / Gilroy, M.P.; Irvine, J.; Riddell, Gideon .

2006. Paper presented at IP Based SOC Design Conference and Exhibition, Grenoble, France.

Research output: Contribution to conference › Paper

TY - CONF

T1 - IP core for hardware RAID 6 acceleration

AU - Gilroy, M.P.

AU - Irvine, J.

AU - Riddell, Gideon

PY - 2006

Y1 - 2006

N2 - As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware

AB - As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures. In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware

KW - IP core

KW - hardware

KW - RAID 6

KW - acceleration

UR - http://www.design-reuse.com/articles/16457/ip-core-for-raid-6-hardware-acceleration.html

M3 - Paper

ER -

Gilroy MP, Irvine J, Riddell G. IP core for hardware RAID 6 acceleration. 2006. Paper presented at IP Based SOC Design Conference and Exhibition, Grenoble, France.

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