Abstract
As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures.
In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware
In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware
| Original language | English |
|---|---|
| Publication status | Published - 2006 |
| Event | IP Based SOC Design Conference and Exhibition - Grenoble, France Duration: 6 Dec 2006 → 7 Dec 2006 |
Conference
| Conference | IP Based SOC Design Conference and Exhibition |
|---|---|
| Abbreviated title | IP/SOC 2006 |
| Country | France |
| City | Grenoble |
| Period | 6/12/06 → 7/12/06 |
Keywords
- IP core
- hardware
- RAID 6
- acceleration
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Cite this
Gilroy, M. P., Irvine, J., & Riddell, G. (2006). IP core for hardware RAID 6 acceleration. Paper presented at IP Based SOC Design Conference and Exhibition, Grenoble, France.