IP core for hardware RAID 6 acceleration

M.P. Gilroy, J. Irvine, Gideon Riddell

Research output: Contribution to conferencePaper

Abstract

As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures.
In this paper we describe the implementation and verification of a RAID 6 IP block. We present an example system implemented on an FPGA to demonstrate the capabilities of the IP block and verify its operation in hardware
Original languageEnglish
Publication statusPublished - 2006
EventIP Based SOC Design Conference and Exhibition - Grenoble, France
Duration: 6 Dec 20067 Dec 2006

Conference

ConferenceIP Based SOC Design Conference and Exhibition
Abbreviated titleIP/SOC 2006
CountryFrance
CityGrenoble
Period6/12/067/12/06

Keywords

  • IP core
  • hardware
  • RAID 6
  • acceleration

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    Gilroy, M. P., Irvine, J., & Riddell, G. (2006). IP core for hardware RAID 6 acceleration. Paper presented at IP Based SOC Design Conference and Exhibition, Grenoble, France.