Intent-preserving FPGA-SoC integration using a design-time metadata intermediate representation (Poster)

Lewis McLaughlin

Intent-preserving FPGA-SoC integration using a design-time metadata intermediate representation (Poster)

Lewis McLaughlin

Electronic And Electrical Engineering

Research output: Contribution to conference › Poster

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Abstract

Domain specialists work with algorithms, sample rates and numeric data types, but may lack FPGA integration expertise. These properties can be lost between Python/Simulink models, IP descriptions, block designs and runtime metadata.

Original language	English
Number of pages	1
Publication status	Published - 14 Sept 2026
Event	IEEE High Performance Extreme Computing (HPEC) - Duration: 14 Sept 2026 → 18 Sept 2026

Conference

Conference	IEEE High Performance Extreme Computing (HPEC)
Period	14/09/26 → 18/09/26

Keywords

FPGA

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McLaughlin-etal-HPEC-2026-Intent-preserving-FPGA-SoC-integration-using-a-design-timeAccepted author manuscript, 1.3 MBLicence: Strath_1

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@conference{053feef2c4f24e60af2d59bc7b09f2bd,

title = "Intent-preserving FPGA-SoC integration using a design-time metadata intermediate representation (Poster)",

abstract = "Domain specialists work with algorithms, sample rates and numeric data types, but may lack FPGA integration expertise. These properties can be lost between Python/Simulink models, IP descriptions, block designs and runtime metadata.",

keywords = "FPGA",

author = "Lewis McLaughlin",

year = "2026",

month = sep,

day = "14",

language = "English",

note = "IEEE High Performance Extreme Computing (HPEC) ; Conference date: 14-09-2026 Through 18-09-2026",

}

TY - CONF

T1 - Intent-preserving FPGA-SoC integration using a design-time metadata intermediate representation (Poster)

AU - McLaughlin, Lewis

PY - 2026/9/14

Y1 - 2026/9/14

N2 - Domain specialists work with algorithms, sample rates and numeric data types, but may lack FPGA integration expertise. These properties can be lost between Python/Simulink models, IP descriptions, block designs and runtime metadata.

AB - Domain specialists work with algorithms, sample rates and numeric data types, but may lack FPGA integration expertise. These properties can be lost between Python/Simulink models, IP descriptions, block designs and runtime metadata.

KW - FPGA

M3 - Poster

T2 - IEEE High Performance Extreme Computing (HPEC)

Y2 - 14 September 2026 through 18 September 2026

ER -

Intent-preserving FPGA-SoC integration using a design-time metadata intermediate representation (Poster)

Abstract

Conference

Keywords

Access to Document

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