Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters

L. Gao, J.E. Fletcher, D. Reay, L. Zheng

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Abstract

The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.

Conference

Conference3rd IET International Conference on Power Electronics, Machines and Drives
Abbreviated titlePEMD 2006
CountryIreland
CityDublin
Period4/04/066/04/06

Fingerprint

Pulse width modulation
Diodes
Capacitors
Electric potential
Field programmable gate arrays (FPGA)
Capacitance
Power MOSFET

Keywords

  • capacitor voltage
  • multi-level inverters
  • voltage ripple

Cite this

Gao, L., Fletcher, J. E., Reay, D., & Zheng, L. (2006). Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters. 378-382. Paper presented at 3rd IET International Conference on Power Electronics, Machines and Drives, Dublin, Ireland. https://doi.org/10.1049/cp:20060135
Gao, L. ; Fletcher, J.E. ; Reay, D. ; Zheng, L. / Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters. Paper presented at 3rd IET International Conference on Power Electronics, Machines and Drives, Dublin, Ireland.5 p.
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abstract = "The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.",
keywords = "capacitor voltage , multi-level inverters , voltage ripple",
author = "L. Gao and J.E. Fletcher and D. Reay and L. Zheng",
year = "2006",
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note = "3rd IET International Conference on Power Electronics, Machines and Drives, PEMD 2006 ; Conference date: 04-04-2006 Through 06-04-2006",

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Gao, L, Fletcher, JE, Reay, D & Zheng, L 2006, 'Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters' Paper presented at 3rd IET International Conference on Power Electronics, Machines and Drives, Dublin, Ireland, 4/04/06 - 6/04/06, pp. 378-382. https://doi.org/10.1049/cp:20060135

Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters. / Gao, L.; Fletcher, J.E.; Reay, D.; Zheng, L.

2006. 378-382 Paper presented at 3rd IET International Conference on Power Electronics, Machines and Drives, Dublin, Ireland.

Research output: Contribution to conferencePaper

TY - CONF

T1 - Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters

AU - Gao, L.

AU - Fletcher, J.E.

AU - Reay, D.

AU - Zheng, L.

PY - 2006

Y1 - 2006

N2 - The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.

AB - The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.

KW - capacitor voltage

KW - multi-level inverters

KW - voltage ripple

U2 - 10.1049/cp:20060135

DO - 10.1049/cp:20060135

M3 - Paper

SP - 378

EP - 382

ER -

Gao L, Fletcher JE, Reay D, Zheng L. Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters. 2006. Paper presented at 3rd IET International Conference on Power Electronics, Machines and Drives, Dublin, Ireland. https://doi.org/10.1049/cp:20060135