Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters

L. Gao, J.E. Fletcher, D. Reay, L. Zheng

Research output: Contribution to conferencePaper

3 Citations (Scopus)

Abstract

The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.
Original languageEnglish
Pages378-382
Number of pages5
DOIs
Publication statusPublished - 2006
Event3rd IET International Conference on Power Electronics, Machines and Drives - Dublin, Ireland
Duration: 4 Apr 20066 Apr 2006

Conference

Conference3rd IET International Conference on Power Electronics, Machines and Drives
Abbreviated titlePEMD 2006
CountryIreland
CityDublin
Period4/04/066/04/06

Keywords

  • capacitor voltage
  • multi-level inverters
  • voltage ripple

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    Gao, L., Fletcher, J. E., Reay, D., & Zheng, L. (2006). Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters. 378-382. Paper presented at 3rd IET International Conference on Power Electronics, Machines and Drives, Dublin, Ireland. https://doi.org/10.1049/cp:20060135