Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters

L. Gao; J.E. Fletcher; D. Reay; L. Zheng

doi:10.1049/cp:20060135

Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters

L. Gao, J.E. Fletcher, D. Reay, L. Zheng

Electronic And Electrical Engineering

Research output: Contribution to conference › Paper

3 Citations (Scopus)

Abstract

The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.

Original language	English
Pages	378-382
Number of pages	5
DOIs	https://doi.org/10.1049/cp:20060135
Publication status	Published - 2006
Event	3rd IET International Conference on Power Electronics, Machines and Drives - Dublin, Ireland Duration: 4 Apr 2006 → 6 Apr 2006

Conference

Conference	3rd IET International Conference on Power Electronics, Machines and Drives
Abbreviated title	PEMD 2006
Country/Territory	Ireland
City	Dublin
Period	4/04/06 → 6/04/06

Keywords

capacitor voltage
multi-level inverters
voltage ripple

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10.1049/cp:20060135

Cite this

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title = "Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters",

abstract = "The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.",

keywords = "capacitor voltage , multi-level inverters , voltage ripple",

author = "L. Gao and J.E. Fletcher and D. Reay and L. Zheng",

year = "2006",

doi = "10.1049/cp:20060135",

language = "English",

pages = "378--382",

note = "3rd IET International Conference on Power Electronics, Machines and Drives, PEMD 2006 ; Conference date: 04-04-2006 Through 06-04-2006",

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TY - CONF

T1 - Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters

AU - Gao, L.

AU - Fletcher, J.E.

AU - Reay, D.

AU - Zheng, L.

PY - 2006

Y1 - 2006

N2 - The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.

AB - The aim of this paper is to show that with three-level multi-phase inverter systems, the extra load connections involved in the inversion process reduce the amplitude and increase the frequency of voltage ripple across the DC link capacitors, assuming the same DC capacitance and the same total power output. Symmetrical regular sampled phase disposition PWM (SRSPDPWM) is employed to generate the PWM signals for the inverter using an Altera cyclone FPGA. A 3-level 5-phase NPC inverter based on power MOSFETs is used to compare the cyclic voltage variation of the 3-level 3-phase system with that of the 3-level 5-phase system.

KW - capacitor voltage

KW - multi-level inverters

KW - voltage ripple

U2 - 10.1049/cp:20060135

DO - 10.1049/cp:20060135

M3 - Paper

SP - 378

EP - 382

T2 - 3rd IET International Conference on Power Electronics, Machines and Drives

Y2 - 4 April 2006 through 6 April 2006

ER -

Improvements in capacitor voltage balancing using multi-phase diode-clamped multi-level inverters

Abstract

Conference

Keywords

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