Implementing the VSIPL API on reconfigurable computers

R. Bruce, M. Devlin, S. Marshall

Research output: Contribution to conferencePaper

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Abstract

FPGA-based reconfigurable computers have widely recognised performance advantages over microprocessor-based systems. One of the greatest impediments to their widespread deployment has been the difficulty inherent in their programming. The authors have looked at the viability of implementing the basic functions of the Vector, Signal, and Image-Processing Library (VSIPL) standard API using reconfigurable computers as the principal compute element. Ideally, such an implementation would offer significant abstraction from the complexities of FPGA design and would allow for high design productivity. Several factors make this impractical in the short term as a path to high-performance reconfigurable computing. In order to maintain standards compliance to VSIPL, performance must be sacrificed. Problems include: the high function-call overheads of FPGA functions; the complexities and overheads of data transfer between the differing memory structures of FPGA and CPU-based systems; the lack of suitable building-block IP to reduce the implementation and verification workload is also an obstacle. The focus of the work has shifted to providing a low-level library of floating-point math functions, analogous to ANSI C’s math.h library. This library can both act as a building block for future implementations of APIs like VSIPL and as a enabler to high-level languages that target FPGAs.
Original languageEnglish
Number of pages6
Publication statusPublished - 2006
Event9th Annual International MAPLD Conference - Washington, D.C., United States
Duration: 26 Sep 200628 Sep 2008

Conference

Conference9th Annual International MAPLD Conference
CountryUnited States
CityWashington, D.C.
Period26/09/0628/09/08

Keywords

  • field-programmable gate arrays,
  • floating-point arithmetic
  • Reconfigurable architectures

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