Implementing algorithms on FPGAs using high-level languages and low-level libraries

R. Bruce, R. Chamberlain, M. Devlin, S. Marshall

Research output: Contribution to conferencePoster

Abstract

Until relatively recently, users of FPGA-based computers have needed electronic-design skills to implement high-performance computing (HPC) algorithms. With the advent of high-level languages for FPGAs it is possible for non-experts in FPGA design to implement algorithms by describing them in a high-level syntax. A natural progression from developing high-level languages is to develop low-level libraries that support them.DIME-C is a high-level language that takes a subset of ANSI C as its input and outputs auto-generated hardware description language (HDL) and pre-synthesised netlists. Within DIME-C, the authors have implemented a math library composed of single-precision, floating-point, elementary functions such as the natural exponential and logarithm. Complex, fully-pipelined algorithms can be described in ANSI-compatible C and implemented on FPGAs, delivering orders of magnitude speed-up over microprocessor implementations. Work is ongoing, expanding the library.The poster will detail project motivations and direction, speedup and resource-use measurements, C-code examples and multi-fpga examples.

Conference

Conference2006 ACM/IEEE conference on Supercomputing
CountryUnited Kingdom
Period4/11/064/11/06

Fingerprint

High level languages
Field programmable gate arrays (FPGA)
Computer hardware description languages
Microprocessor chips

Keywords

  • implementing algorithms
  • fpga
  • high-level languages
  • low-level libraries

Cite this

Bruce, R., Chamberlain, R., Devlin, M., & Marshall, S. (2006). Implementing algorithms on FPGAs using high-level languages and low-level libraries. Poster session presented at 2006 ACM/IEEE conference on Supercomputing , United Kingdom. https://doi.org/10.1145/1188455.1188614
Bruce, R. ; Chamberlain, R. ; Devlin, M. ; Marshall, S. / Implementing algorithms on FPGAs using high-level languages and low-level libraries. Poster session presented at 2006 ACM/IEEE conference on Supercomputing , United Kingdom.
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Bruce, R, Chamberlain, R, Devlin, M & Marshall, S 2006, 'Implementing algorithms on FPGAs using high-level languages and low-level libraries' 2006 ACM/IEEE conference on Supercomputing , United Kingdom, 4/11/06 - 4/11/06, . https://doi.org/10.1145/1188455.1188614

Implementing algorithms on FPGAs using high-level languages and low-level libraries. / Bruce, R.; Chamberlain, R.; Devlin, M.; Marshall, S.

2006. Poster session presented at 2006 ACM/IEEE conference on Supercomputing , United Kingdom.

Research output: Contribution to conferencePoster

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AU - Chamberlain, R.

AU - Devlin, M.

AU - Marshall, S.

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AB - Until relatively recently, users of FPGA-based computers have needed electronic-design skills to implement high-performance computing (HPC) algorithms. With the advent of high-level languages for FPGAs it is possible for non-experts in FPGA design to implement algorithms by describing them in a high-level syntax. A natural progression from developing high-level languages is to develop low-level libraries that support them.DIME-C is a high-level language that takes a subset of ANSI C as its input and outputs auto-generated hardware description language (HDL) and pre-synthesised netlists. Within DIME-C, the authors have implemented a math library composed of single-precision, floating-point, elementary functions such as the natural exponential and logarithm. Complex, fully-pipelined algorithms can be described in ANSI-compatible C and implemented on FPGAs, delivering orders of magnitude speed-up over microprocessor implementations. Work is ongoing, expanding the library.The poster will detail project motivations and direction, speedup and resource-use measurements, C-code examples and multi-fpga examples.

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KW - low-level libraries

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Bruce R, Chamberlain R, Devlin M, Marshall S. Implementing algorithms on FPGAs using high-level languages and low-level libraries. 2006. Poster session presented at 2006 ACM/IEEE conference on Supercomputing , United Kingdom. https://doi.org/10.1145/1188455.1188614