Abstract
A hybrid MMC with reduced three-level (TL) cells is proposed. As well as the dc fault blocking capability, the proposed hybrid MMC provides the benefits of: lower conduction losses; fewer diode and switching devices, and; fewer shoot-through modes. Guidelines are developed to determine the required number of three-level cells to block a dc-side fault. It is also demonstrated that a further reduction in the number a three-level cells is possible if a rise in cell current and voltage is acceptable. This reduction is investigated. A lower number of three-level cells reduces losses and capital cost further. The hybrid MMC with the reduced number of three-level cells proves to be the most attractive approach compared with other MMCs and hybrid MMCs. The semiconductor count and conduction loss are 92.1% and 90.3% respectively of that of the MMC based entirely on full-bridge cells, without exposing the semiconductors to significant fault currents and over-voltages. The simulation results demonstrate the feasibility of the proposed hybrid converter.
Original language | English |
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Title of host publication | 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia) |
Publisher | IEEE |
ISBN (Electronic) | 9781509012107 |
ISBN (Print) | 9781509012114 |
DOIs | |
Publication status | Published - 22 May 2016 |
Event | 8th International Power Electronics and Motion Control Conference-ECCE Asia(IPEMC 2016-ECCE Asia) - Platinum Hanjue Hotel, Hefei, China Duration: 22 May 2016 → 25 May 2016 http://www.ipemc2016.org/index.php |
Conference
Conference | 8th International Power Electronics and Motion Control Conference-ECCE Asia(IPEMC 2016-ECCE Asia) |
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Country/Territory | China |
City | Hefei |
Period | 22/05/16 → 25/05/16 |
Internet address |
Keywords
- dc fault blocking
- HVDC transmission
- hybrid modular multilevel converter (MMC)
- fault currents
- capacitors
- circuit faults
- hidden Markov models
- capacitance
- stress