High temperature nanoscratching of single crystal silicon under reduced oxygen condition

Saeed Zare Chavoshi, Santiago Corujeira Gallo, Hanshan Dong, Xichun Luo

Research output: Contribution to journalArticle

15 Citations (Scopus)

Abstract

In-situ high temperature nanoscratching of Si(110) wafer under reduced oxygen condition was carried out for the first time using a Berkovich tip with a ramp load at low and high scratching speeds. Ex-situ Raman spectroscopy and AFM analysis were performed to characterize high pressure phase transformation, nanoscratch topography and nanoscratch hardness. No remnants of high pressure silicon phases were observed along all the nanoscratch residual tracks in high temperature nanoscratching, whereas in room temperature nanoscratching, phase transformation showed a significant dependence on the applied load and scratching speed i.e. the deformed volume inside the nanoscratch made at room temperature was comprised of Si-I, Si-XII and Si-III above different threshold loads at low and high scratching speeds. Further analysis through AFM measurements demonstrated that the scratch hardness and residual scratch morphologies i.e. scratch depth, scratch width and total pile-up heights are greatly affected by the wafer temperature and scratching speed.
LanguageEnglish
Pages385-293
Number of pages9
JournalMaterials Science and Engineering: A
Volume684
Early online date29 Nov 2016
DOIs
Publication statusPublished - 27 Jan 2017

Fingerprint

Silicon
Single crystals
Oxygen
phase transformations
single crystals
silicon
oxygen
hardness
high speed
atomic force microscopy
wafers
room temperature
piles
ramps
Temperature
Phase transitions
Hardness
topography
Raman spectroscopy
thresholds

Keywords

  • high temperature
  • nanoscratching
  • single crystal silicon
  • polymorphs
  • fracture toughness
  • hardness
  • plastic deformation
  • machinability
  • molecular dynamics simulation

Cite this

Zare Chavoshi, Saeed ; Gallo, Santiago Corujeira ; Dong, Hanshan ; Luo, Xichun. / High temperature nanoscratching of single crystal silicon under reduced oxygen condition. In: Materials Science and Engineering: A. 2017 ; Vol. 684. pp. 385-293.
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High temperature nanoscratching of single crystal silicon under reduced oxygen condition. / Zare Chavoshi, Saeed; Gallo, Santiago Corujeira; Dong, Hanshan; Luo, Xichun.

In: Materials Science and Engineering: A, Vol. 684, 27.01.2017, p. 385-293.

Research output: Contribution to journalArticle

TY - JOUR

T1 - High temperature nanoscratching of single crystal silicon under reduced oxygen condition

AU - Zare Chavoshi, Saeed

AU - Gallo, Santiago Corujeira

AU - Dong, Hanshan

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N2 - In-situ high temperature nanoscratching of Si(110) wafer under reduced oxygen condition was carried out for the first time using a Berkovich tip with a ramp load at low and high scratching speeds. Ex-situ Raman spectroscopy and AFM analysis were performed to characterize high pressure phase transformation, nanoscratch topography and nanoscratch hardness. No remnants of high pressure silicon phases were observed along all the nanoscratch residual tracks in high temperature nanoscratching, whereas in room temperature nanoscratching, phase transformation showed a significant dependence on the applied load and scratching speed i.e. the deformed volume inside the nanoscratch made at room temperature was comprised of Si-I, Si-XII and Si-III above different threshold loads at low and high scratching speeds. Further analysis through AFM measurements demonstrated that the scratch hardness and residual scratch morphologies i.e. scratch depth, scratch width and total pile-up heights are greatly affected by the wafer temperature and scratching speed.

AB - In-situ high temperature nanoscratching of Si(110) wafer under reduced oxygen condition was carried out for the first time using a Berkovich tip with a ramp load at low and high scratching speeds. Ex-situ Raman spectroscopy and AFM analysis were performed to characterize high pressure phase transformation, nanoscratch topography and nanoscratch hardness. No remnants of high pressure silicon phases were observed along all the nanoscratch residual tracks in high temperature nanoscratching, whereas in room temperature nanoscratching, phase transformation showed a significant dependence on the applied load and scratching speed i.e. the deformed volume inside the nanoscratch made at room temperature was comprised of Si-I, Si-XII and Si-III above different threshold loads at low and high scratching speeds. Further analysis through AFM measurements demonstrated that the scratch hardness and residual scratch morphologies i.e. scratch depth, scratch width and total pile-up heights are greatly affected by the wafer temperature and scratching speed.

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