High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs

Philip Anthony; Neville McNeill; Derrick Holliday

doi:10.1109/ECCE.2012.6342520

High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs

Philip Anthony, Neville McNeill, Derrick Holliday

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

21 Citations (Scopus)

Abstract

Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 μJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.

Original language	English
Title of host publication	2012 IEEE Energy Conversion Congress and Exposition (ECCE)
Place of Publication	Piscataway, N.J.
Publisher	IEEE
Pages	2961-2968
Number of pages	8
ISBN (Print)	978-1-4673-0802-1
DOIs	https://doi.org/10.1109/ECCE.2012.6342520
Publication status	Published - 15 Sep 2012
Event	4th IEEE Energy Conversion Congress and Exposition - Duration: 1 Sep 2012 → 30 Sep 2012

Conference

Conference	4th IEEE Energy Conversion Congress and Exposition
Period	1/09/12 → 30/09/12

Keywords

logic gates
switching loss
wide band gap semiconductors

Access to Document

10.1109/ECCE.2012.6342520

http://ieeexplore.ieee.org/document/6342520/

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Cite this

@inproceedings{25bdc74f23d94b5e9d6fdf9068e45a3c,

title = "High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs",

abstract = "Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 μJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.",

keywords = "logic gates, switching loss, wide band gap semiconductors",

author = "Philip Anthony and Neville McNeill and Derrick Holliday",

year = "2012",

month = sep,

day = "15",

doi = "10.1109/ECCE.2012.6342520",

language = "English",

isbn = "978-1-4673-0802-1",

pages = "2961--2968",

booktitle = "2012 IEEE Energy Conversion Congress and Exposition (ECCE)",

publisher = "IEEE",

note = "4th IEEE Energy Conversion Congress and Exposition ; Conference date: 01-09-2012 Through 30-09-2012",

}

TY - GEN

T1 - High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs

AU - Anthony, Philip

AU - McNeill, Neville

AU - Holliday, Derrick

PY - 2012/9/15

Y1 - 2012/9/15

N2 - Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 μJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.

AB - Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 μJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.

KW - logic gates

KW - switching loss

KW - wide band gap semiconductors

UR - http://ieeexplore.ieee.org/document/6342520/

U2 - 10.1109/ECCE.2012.6342520

DO - 10.1109/ECCE.2012.6342520

M3 - Conference contribution book

SN - 978-1-4673-0802-1

SP - 2961

EP - 2968

BT - 2012 IEEE Energy Conversion Congress and Exposition (ECCE)

PB - IEEE

CY - Piscataway, N.J.

T2 - 4th IEEE Energy Conversion Congress and Exposition

Y2 - 1 September 2012 through 30 September 2012

ER -