Harmonic-by-harmonic time delay compensation Method for PHIL simulation of low impedance power systems

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

3 Citations (Scopus)

Abstract

In PHIL simulations different time delays are introduced. Although it can be reduced, there is always some time delay. As a consequence, when the device under test is part of a low impedance power system such as: microgrids, marine or aero power systems, the simulation process becomes challenging due to the poor accuracy of the results achieved by the introduction of the time delay. Therefore, in order to accurately compensate for the inherent time delay introduced in Power Hardware in the Loop (PHIL) simulations, a method based on phase-shifting the reference voltage signal harmonic-by-harmonic and phase-by-phase is proposed. In this manner the time delay compensation will not affect to the system topology and therefore the dynamic behaviour of the original system will stay as it originally was in terms of power angles and V-I phase relationships for all the harmonics processed. In this paper, an experiment where the reference voltage is altered with 5th and 7th harmonics shows that the accuracy of PHIL simulations after the application of this compensation method is greatly improved compared with traditional methods. As a result, low impedance power systems are now able to experience an accurate PHIL simulation.
LanguageEnglish
Title of host publicationProceedings of the 2015 International Symposium on Smart Electric Distribution Systems and Technologies (EDST)
PublisherIEEE
Pages560-565
Number of pages6
ISBN (Print)978-1-4799-7736-9
DOIs
Publication statusPublished - Sep 2015
EventInternational Symposium on Smart Electric Distribution Systems and Technologies (EDST) - Vienna, Austria
Duration: 8 Sep 201511 Sep 2015

Conference

ConferenceInternational Symposium on Smart Electric Distribution Systems and Technologies (EDST)
CountryAustria
CityVienna
Period8/09/1511/09/15

Fingerprint

Time delay
Hardware
Electric potential
Topology
Compensation and Redress
Experiments

Keywords

  • harmonic compensation
  • accuracy
  • low impedance power system
  • power hardware in the loop
  • real time simulation
  • simulation time delay

Cite this

Guillo Sansano, E., Roscoe, A. J., & Burt, G. M. (2015). Harmonic-by-harmonic time delay compensation Method for PHIL simulation of low impedance power systems. In Proceedings of the 2015 International Symposium on Smart Electric Distribution Systems and Technologies (EDST) (pp. 560-565). IEEE. https://doi.org/10.1109/SEDST.2015.7315271
Guillo Sansano, E. ; Roscoe, A.J. ; Burt, G.M. / Harmonic-by-harmonic time delay compensation Method for PHIL simulation of low impedance power systems. Proceedings of the 2015 International Symposium on Smart Electric Distribution Systems and Technologies (EDST). IEEE, 2015. pp. 560-565
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Guillo Sansano, E, Roscoe, AJ & Burt, GM 2015, Harmonic-by-harmonic time delay compensation Method for PHIL simulation of low impedance power systems. in Proceedings of the 2015 International Symposium on Smart Electric Distribution Systems and Technologies (EDST). IEEE, pp. 560-565, International Symposium on Smart Electric Distribution Systems and Technologies (EDST), Vienna, Austria, 8/09/15. https://doi.org/10.1109/SEDST.2015.7315271

Harmonic-by-harmonic time delay compensation Method for PHIL simulation of low impedance power systems. / Guillo Sansano, E.; Roscoe, A.J.; Burt, G.M.

Proceedings of the 2015 International Symposium on Smart Electric Distribution Systems and Technologies (EDST). IEEE, 2015. p. 560-565.

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

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Guillo Sansano E, Roscoe AJ, Burt GM. Harmonic-by-harmonic time delay compensation Method for PHIL simulation of low impedance power systems. In Proceedings of the 2015 International Symposium on Smart Electric Distribution Systems and Technologies (EDST). IEEE. 2015. p. 560-565 https://doi.org/10.1109/SEDST.2015.7315271