Hardware co-simulation in system generator of the AES-128 encryption algorithm

D.J. Denning, M. Devlin, J. Irvine

Research output: Contribution to conferencePaper

Abstract

We discuss the use of System Generator to hardware co-simulate in the FPGA versions of the AES-128 encryption algorithm. We show that the FPGA co-simulation of the AES can be achieved over 3 different bus types (TCP/IP, board-level TCP/IP, and PCI). One of the FPGA co-simulations is over 3 times faster running over a TCP/IP network distance off approximately 600 kilometres, than running a normal Simulink simulation on the host PC. Another hardware co-simulation time increases in the region of 4000% running over the PCI bus attached to the host PC. By having this FPGA co-simulation option, some of the IP cores in an FPGA system can be co-simulated, there by freeing up processing power on the host-PC for further developments in a system.
Original languageEnglish
Pages247-247
Number of pages1
DOIs
Publication statusPublished - 2004
EventACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays - Monterey, California, United States
Duration: 22 Feb 200423 Feb 2004

Conference

ConferenceACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays
Abbreviated titleFPGA 2004
CountryUnited States
CityMonterey, California
Period22/02/0423/02/04

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Keywords

  • hardware
  • co-simulation
  • system generator
  • AES-128
  • encryption algorithm

Cite this

Denning, D. J., Devlin, M., & Irvine, J. (2004). Hardware co-simulation in system generator of the AES-128 encryption algorithm. 247-247. Paper presented at ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, Monterey, California, United States. https://doi.org/10.1145/968280.968322