Full custom design of an arbitrary waveform gate driver with 10 GHz waypoint rates for GaN FETs

Active gate driving of power devices seeks to shape switching trajectories via the gate, for example to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex gate signals. In this paper, we describe for the first time the implementation details of a digitally programmable arbitrary waveform gate driver capable of a 10 GHz waypoint rate, including comprehensive design considerations for critical high-speed subsystems that codify the trade-off in flexibility, speed and area. Our design, which is taped out in a 180 nm high-voltage CMOS process, utilises buffers that switch up to ten times in a single clock cycle to overcome the limited achievable clock-speed of high-voltage silicon integrated circuits, and a fully digital architecture to provide robustness under high slew-rates of the ground rail. The driver IC has networks of 100 ps delay elements that are digitally configured prior to a switching transient, to selectively control an array of fast, parallel-connected drivers with different output impedances. Key to the high timing resolution are high-speed asynchronous circuits for memory readout, output buffering and pulse generation. The driver IC is experimentally evaluated to have a 100 ps resolution, and to operate reliably in a 400 V GaN bridge leg, under ground-rail voltage slew rates peaking at over 100 V/ns. Design rules are provided to obtain an architecture with the least area for a given set of timing and impedance resolution requirements. The reported design methods enable complex driving waveforms to be applied during nanosecond-scale transients of GaN power devices and demonstrate how digitally-programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.