FPGA implementation of a memory-efficient Hough Parameter Space for the detection of lines

David Northcote; Louise H. Crockett; Paul Murray

doi:10.1109/ISCAS.2018.8351115

FPGA implementation of a memory-efficient Hough Parameter Space for the detection of lines

David Northcote
, Louise H. Crockett
, Paul Murray

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

5 Citations (Scopus)

110 Downloads (Pure)

Abstract

The Line Hough Transform (LHT) is a robust and accurate line detection algorithm, useful for applications such as lane detection in Advanced Driver Assistance Systems. For real-time implementation, the LHT is demanding in terms of computation and memory, and hence Field Programmable Gate Arrays (FPGAs) are often deployed. However, many small FPGAs are incapable of implementing the LHT due to the large memory requirement of the Hough Parameter Space (HPS). This paper presents a memory-efficient architecture of the LHT named the Angular Regions - Line Hough Transform (AR-LHT). We present a suitable FPGA implementation of the AR-LHT and provide a performance and resource analysis after targeting a Xilinx xc7z010-1 device. Results demonstrate that, for an image of 1024x1024 pixels, approximately 48% less memory is used than the Standard LHT. The FPGA architecture is capable of processing a single image in 9.03ms.

Original language	English
Title of host publication	2018 IEEE International Symposium on Circuits and Systems (ISCAS)
Place of Publication	Piscataway, N.J.
Publisher	IEEE
Number of pages	5
ISBN (Print)	978-1-5386-4882-7
DOIs	https://doi.org/10.1109/ISCAS.2018.8351115
Publication status	Published - 4 May 2018
Event	IEEE International Symposium on Circuits & Systems 2018 - Firenze Fiera Congress & Exhibition Center, Florence, Italy Duration: 27 May 2018 → 30 May 2018 Conference number: 41626 http://www.iscas2018.org/

Conference

Conference	IEEE International Symposium on Circuits & Systems 2018
Abbreviated title	ISCAS 2018
Country/Territory	Italy
City	Florence
Period	27/05/18 → 30/05/18
Internet address	http://www.iscas2018.org/

Keywords

FPGA
Hough transform
line detection
memory-efficient
computer vision
angular regions

Access to Document

10.1109/ISCAS.2018.8351115

Northcote-etal-ISCAS2018-FPGA-implementation-of-a-memory-efficient-Hough-Parameter-SpaceAccepted author manuscript, 1.28 MB

Cite this

@inproceedings{f800f6f5c63c4464b4936b118f2a7965,

title = "FPGA implementation of a memory-efficient Hough Parameter Space for the detection of lines",

abstract = "The Line Hough Transform (LHT) is a robust and accurate line detection algorithm, useful for applications such as lane detection in Advanced Driver Assistance Systems. For real-time implementation, the LHT is demanding in terms of computation and memory, and hence Field Programmable Gate Arrays (FPGAs) are often deployed. However, many small FPGAs are incapable of implementing the LHT due to the large memory requirement of the Hough Parameter Space (HPS). This paper presents a memory-efficient architecture of the LHT named the Angular Regions - Line Hough Transform (AR-LHT). We present a suitable FPGA implementation of the AR-LHT and provide a performance and resource analysis after targeting a Xilinx xc7z010-1 device. Results demonstrate that, for an image of 1024x1024 pixels, approximately 48\% less memory is used than the Standard LHT. The FPGA architecture is capable of processing a single image in 9.03ms.",

keywords = "FPGA, Hough transform, line detection, memory-efficient, computer vision, angular regions",

author = "David Northcote and Crockett, \{Louise H.\} and Paul Murray",

note = "{\textcopyright} 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.; IEEE International Symposium on Circuits \& Systems 2018, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",

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booktitle = "2018 IEEE International Symposium on Circuits and Systems (ISCAS)",

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TY - GEN

T1 - FPGA implementation of a memory-efficient Hough Parameter Space for the detection of lines

AU - Northcote, David

AU - Crockett, Louise H.

AU - Murray, Paul

N1 - Conference code: 41626

PY - 2018/5/4

Y1 - 2018/5/4

N2 - The Line Hough Transform (LHT) is a robust and accurate line detection algorithm, useful for applications such as lane detection in Advanced Driver Assistance Systems. For real-time implementation, the LHT is demanding in terms of computation and memory, and hence Field Programmable Gate Arrays (FPGAs) are often deployed. However, many small FPGAs are incapable of implementing the LHT due to the large memory requirement of the Hough Parameter Space (HPS). This paper presents a memory-efficient architecture of the LHT named the Angular Regions - Line Hough Transform (AR-LHT). We present a suitable FPGA implementation of the AR-LHT and provide a performance and resource analysis after targeting a Xilinx xc7z010-1 device. Results demonstrate that, for an image of 1024x1024 pixels, approximately 48% less memory is used than the Standard LHT. The FPGA architecture is capable of processing a single image in 9.03ms.

AB - The Line Hough Transform (LHT) is a robust and accurate line detection algorithm, useful for applications such as lane detection in Advanced Driver Assistance Systems. For real-time implementation, the LHT is demanding in terms of computation and memory, and hence Field Programmable Gate Arrays (FPGAs) are often deployed. However, many small FPGAs are incapable of implementing the LHT due to the large memory requirement of the Hough Parameter Space (HPS). This paper presents a memory-efficient architecture of the LHT named the Angular Regions - Line Hough Transform (AR-LHT). We present a suitable FPGA implementation of the AR-LHT and provide a performance and resource analysis after targeting a Xilinx xc7z010-1 device. Results demonstrate that, for an image of 1024x1024 pixels, approximately 48% less memory is used than the Standard LHT. The FPGA architecture is capable of processing a single image in 9.03ms.

KW - FPGA

KW - Hough transform

KW - line detection

KW - memory-efficient

KW - computer vision

KW - angular regions

UR - http://www.iscas2018.org/

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DO - 10.1109/ISCAS.2018.8351115

M3 - Conference contribution book

SN - 978-1-5386-4882-7

BT - 2018 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - IEEE

CY - Piscataway, N.J.

T2 - IEEE International Symposium on Circuits & Systems 2018

Y2 - 27 May 2018 through 30 May 2018

ER -

FPGA implementation of a memory-efficient Hough Parameter Space for the detection of lines

Abstract

Conference

Keywords

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Doctoral Training Partnership (DTP - University of Strathclyde) | Northcote, David

Angular Regions - Line Hough Transform (AR-LHT) Implementation on Field Programmable Gate Array (FPGA)

Best Student Paper Award