FPGA implementation of a cyclostationary detector for OFDM signals

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Abstract

Due to the ubiquity of Orthogonal Frequency Division Multiplexing (OFDM) based communications standards such as IEEE 802.11 a/g/n and 3GPP Long Term Evolution (LTE), a growing interest has developed in techniques for reliably detecting the presence of these signals in dynamic radio systems. A popular approach for detection is to exploit the cyclostationary nature of OFDM communications signals. In this paper, we focus on a frequency domain cyclostationary detection algorithm first introduced by Giannakis and Dandawate and study its performance in detecting IEEE 802.11a OFDM signals in the presence of practical radio impairments such as Carrier Frequency offset (CFO), Phase Noise, I/Q Imbalance, Multipath Fading and DC offset. We then present a hardware implementation of this algorithm developed using MathWorks HDL Coder and provide implementation results after targeting to a Xilinx 7 Series FPGA device.
Original languageEnglish
Number of pages5
Publication statusPublished - 7 Sep 2016
EventThe 2016 European Signal Processing Conference - Hotel Hilton Budapest, Budapest, Hungary
Duration: 29 Aug 20162 Sep 2016
Conference number: 37884X
http://www.eusipco2016.org/en_GB

Conference

ConferenceThe 2016 European Signal Processing Conference
Abbreviated titleEUSIPCO 2016
CountryHungary
CityBudapest
Period29/08/162/09/16
Internet address

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Keywords

  • OFDM
  • cyclostationary detection
  • HDL Coder
  • FPGA

Cite this

Allan, D., Crockett, L., Weiss, S., Stuart , K., & Stewart, R. W. (2016). FPGA implementation of a cyclostationary detector for OFDM signals. Paper presented at The 2016 European Signal Processing Conference , Budapest, Hungary.