FPGA implementation of a cyclostationary detector for OFDM signals

Douglas Allan; Louise Crockett; Stephan Weiss; Kenneth Stuart; Robert W. Stewart

FPGA implementation of a cyclostationary detector for OFDM signals

Douglas Allan, Louise Crockett, Stephan Weiss, Kenneth Stuart , Robert W. Stewart

Electronic And Electrical Engineering

Research output: Contribution to conference › Paper

3 Citations (Scopus)

198 Downloads (Pure)

Abstract

Due to the ubiquity of Orthogonal Frequency Division Multiplexing (OFDM) based communications standards such as IEEE 802.11 a/g/n and 3GPP Long Term Evolution (LTE), a growing interest has developed in techniques for reliably detecting the presence of these signals in dynamic radio systems. A popular approach for detection is to exploit the cyclostationary nature of OFDM communications signals. In this paper, we focus on a frequency domain cyclostationary detection algorithm first introduced by Giannakis and Dandawate and study its performance in detecting IEEE 802.11a OFDM signals in the presence of practical radio impairments such as Carrier Frequency offset (CFO), Phase Noise, I/Q Imbalance, Multipath Fading and DC offset. We then present a hardware implementation of this algorithm developed using MathWorks HDL Coder and provide implementation results after targeting to a Xilinx 7 Series FPGA device.

Original language	English
Number of pages	5
Publication status	Published - 7 Sep 2016
Event	The 2016 European Signal Processing Conference - Hotel Hilton Budapest, Budapest, Hungary Duration: 29 Aug 2016 → 2 Sep 2016 Conference number: 37884X http://www.eusipco2016.org/en_GB

Conference

Conference	The 2016 European Signal Processing Conference
Abbreviated title	EUSIPCO 2016
Country	Hungary
City	Budapest
Period	29/08/16 → 2/09/16
Internet address	http://www.eusipco2016.org/en_GB

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Keywords

OFDM
cyclostationary detection
HDL Coder
FPGA

Cite this

Allan, D., Crockett, L., Weiss, S., Stuart , K., & Stewart, R. W. (2016). FPGA implementation of a cyclostationary detector for OFDM signals. Paper presented at The 2016 European Signal Processing Conference , Budapest, Hungary.

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title = "FPGA implementation of a cyclostationary detector for OFDM signals",

abstract = "Due to the ubiquity of Orthogonal Frequency Division Multiplexing (OFDM) based communications standards such as IEEE 802.11 a/g/n and 3GPP Long Term Evolution (LTE), a growing interest has developed in techniques for reliably detecting the presence of these signals in dynamic radio systems. A popular approach for detection is to exploit the cyclostationary nature of OFDM communications signals. In this paper, we focus on a frequency domain cyclostationary detection algorithm first introduced by Giannakis and Dandawate and study its performance in detecting IEEE 802.11a OFDM signals in the presence of practical radio impairments such as Carrier Frequency offset (CFO), Phase Noise, I/Q Imbalance, Multipath Fading and DC offset. We then present a hardware implementation of this algorithm developed using MathWorks HDL Coder and provide implementation results after targeting to a Xilinx 7 Series FPGA device.",

keywords = "OFDM, cyclostationary detection, HDL Coder, FPGA",

author = "Douglas Allan and Louise Crockett and Stephan Weiss and Kenneth Stuart and Stewart, {Robert W.}",

note = "First published in the Proceedings of the 24th European Signal Processing Conference (EUSIPCO-2016) in 2016, published by EURASIP.; The 2016 European Signal Processing Conference , EUSIPCO 2016 ; Conference date: 29-08-2016 Through 02-09-2016",

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AU - Allan, Douglas

AU - Crockett, Louise

AU - Weiss, Stephan

AU - Stuart , Kenneth

AU - Stewart, Robert W.

N1 - First published in the Proceedings of the 24th European Signal Processing Conference (EUSIPCO-2016) in 2016, published by EURASIP.

PY - 2016/9/7

Y1 - 2016/9/7

N2 - Due to the ubiquity of Orthogonal Frequency Division Multiplexing (OFDM) based communications standards such as IEEE 802.11 a/g/n and 3GPP Long Term Evolution (LTE), a growing interest has developed in techniques for reliably detecting the presence of these signals in dynamic radio systems. A popular approach for detection is to exploit the cyclostationary nature of OFDM communications signals. In this paper, we focus on a frequency domain cyclostationary detection algorithm first introduced by Giannakis and Dandawate and study its performance in detecting IEEE 802.11a OFDM signals in the presence of practical radio impairments such as Carrier Frequency offset (CFO), Phase Noise, I/Q Imbalance, Multipath Fading and DC offset. We then present a hardware implementation of this algorithm developed using MathWorks HDL Coder and provide implementation results after targeting to a Xilinx 7 Series FPGA device.

AB - Due to the ubiquity of Orthogonal Frequency Division Multiplexing (OFDM) based communications standards such as IEEE 802.11 a/g/n and 3GPP Long Term Evolution (LTE), a growing interest has developed in techniques for reliably detecting the presence of these signals in dynamic radio systems. A popular approach for detection is to exploit the cyclostationary nature of OFDM communications signals. In this paper, we focus on a frequency domain cyclostationary detection algorithm first introduced by Giannakis and Dandawate and study its performance in detecting IEEE 802.11a OFDM signals in the presence of practical radio impairments such as Carrier Frequency offset (CFO), Phase Noise, I/Q Imbalance, Multipath Fading and DC offset. We then present a hardware implementation of this algorithm developed using MathWorks HDL Coder and provide implementation results after targeting to a Xilinx 7 Series FPGA device.

KW - OFDM

KW - cyclostationary detection

KW - HDL Coder

KW - FPGA

UR - http://www.eusipco2016.org/

M3 - Paper

ER -

Access to Document

Allan-etal-EUSIPCO-2016-FPGA-implementation-of-a-cyclostationary-detector-for-OFDM-signalsAccepted author manuscript, 626 KB

http://www.eusipco2016.org/