Evaluation of a network on chip architecture based on the clockwork routed manhattan street network using hardware emulation

Trends in integrated circuit design indicate a shift in focus from computation to communication. Interconnect issues within devices now come to the fore as the dedicated wire and shared-bus architectures look increasingly ill-equipped to cope with such complexity. This paper proposes a scalable network on chip architecture based on the Manhattan street network (MSN) using clockwork (CW) routing scheme. The proposed solution is self routing and allows for the implementation of routing functionality in hardware, eliminating the need for custom routing tables at each node. In this study, the characteristics of the proposed architecture are evaluated based upon the first full hardware implementation of a functional MSN-CW. Due to the deterministic nature of the routing mechanism, upper bounds on network delay can be established. This makes the architectures particularly suited to applications involving realtime constraints