Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest continues to operate unaffected. As a result, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock
frequency. However, that is beyond the current functionality of Xilinx-based PR as the clock components such as Digital Clock Managers (DCMs) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and clock frequency with ease. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design. The results presented are based on the Xilinx ISE 12.4 design suite and the Xilinx Virtex-5 LX110T device.
|Conference||Software Defined Radio (SDR) Forum (Europe)|
|Period||22/06/11 → 24/06/11|
- reconfiguration technologies
- radio system