Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance

Dawei Liu, Simon J. Hollis, Harry C. P. Dymond, Neville McNeill, Bernard H. Stark

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16 Citations (Scopus)
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A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.
Original languageEnglish
Pages (from-to)688-692
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number7
Early online date18 Feb 2016
Publication statusPublished - 31 Jul 2016


  • low power
  • area efficient
  • dV/dt slewing immunity
  • energy-efficiency
  • floating level shifter
  • high speed
  • clamps
  • delays
  • rails
  • latches
  • logic gates
  • low voltage
  • layout


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