Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance

Dawei Liu, Simon J. Hollis, Harry C. P. Dymond, Neville McNeill, Bernard H. Stark

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.
LanguageEnglish
Pages688-692
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume63
Issue number7
Early online date18 Feb 2016
DOIs
Publication statusPublished - 31 Jul 2016

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Electric potential
Rails
Energy dissipation
Energy conservation
Mirrors
Electric power utilization
Energy utilization
Bandwidth

Keywords

  • low power
  • area efficient
  • dV/dt slewing immunity
  • energy-efficiency
  • floating level shifter
  • high speed
  • clamps
  • delays
  • rails
  • latches
  • logic gates
  • low voltage
  • layout

Cite this

Liu, Dawei ; Hollis, Simon J. ; Dymond, Harry C. P. ; McNeill, Neville ; Stark, Bernard H. / Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance. In: IEEE Transactions on Circuits and Systems II: Express Briefs. 2016 ; Vol. 63, No. 7. pp. 688-692.
@article{83bbe796fe064966a06bcc6a43946c51,
title = "Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance",
abstract = "A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.",
keywords = "low power, area efficient, dV/dt slewing immunity, energy-efficiency, floating level shifter, high speed, clamps, delays, rails, latches, logic gates, low voltage, layout",
author = "Dawei Liu and Hollis, {Simon J.} and Dymond, {Harry C. P.} and Neville McNeill and Stark, {Bernard H.}",
note = "{\circledC} 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.",
year = "2016",
month = "7",
day = "31",
doi = "10.1109/TCSII.2016.2530902",
language = "English",
volume = "63",
pages = "688--692",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-7747",
number = "7",

}

Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance. / Liu, Dawei; Hollis, Simon J.; Dymond, Harry C. P.; McNeill, Neville; Stark, Bernard H.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 7, 31.07.2016, p. 688-692.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Design of 370-ps delay floating voltage level shifters with 30 V/ns power supply slew tolerance

AU - Liu, Dawei

AU - Hollis, Simon J.

AU - Dymond, Harry C. P.

AU - McNeill, Neville

AU - Stark, Bernard H.

N1 - © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

PY - 2016/7/31

Y1 - 2016/7/31

N2 - A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.

AB - A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.

KW - low power

KW - area efficient

KW - dV/dt slewing immunity

KW - energy-efficiency

KW - floating level shifter

KW - high speed

KW - clamps

KW - delays

KW - rails

KW - latches

KW - logic gates

KW - low voltage

KW - layout

UR - https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8920

U2 - 10.1109/TCSII.2016.2530902

DO - 10.1109/TCSII.2016.2530902

M3 - Article

VL - 63

SP - 688

EP - 692

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

T2 - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-7747

IS - 7

ER -