DC fault parameter sensitivity analysis

Frederick Page; Grain Adam; Stephen Finney; Derrick Holliday; Lie Xu

doi:10.1049/cp.2014.0014

DC fault parameter sensitivity analysis

Frederick Page, Grain Adam, Stephen Finney, Derrick Holliday, Lie Xu

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

7 Citations (Scopus)

167 Downloads (Pure)

Abstract

At present High Voltage Direct Current (HVDC) Voltage Source Converters (VSC) are susceptible dc faults leading to extreme currents. The fault current cannot be controlled by the converter switching flows in the anti-parallel diodes. Protection devices are, therefore, required to operate with sufficient speed to avoid device failure. A method is introduced to calculate the critical time for protection to operate. Using this method it is then shown how the critical time may be extended by way of optimization of passive system components. In order to perform this optimization a new post-fault (when the converter gating signals are inhibited) model of the Modular Multi-Level (MMC) converter is introduced which drastically reduces simulation time, allowing high resolution parameter sweeps to be performed. The model is validated and is shown to produce fault characteristics similar to that of a conventional switched model.

Original language	English
Title of host publication	Proceedings of the 12th IET International Conference on Developments in Power System Protection (DPSP 2014)
Place of Publication	Stevenage, UK
Publisher	Institution of Engineering and Technology
Number of pages	6
Volume	2014
ISBN (Print)	9781849198349
DOIs	https://doi.org/10.1049/cp.2014.0014
Publication status	Published - 2014
Event	12th IET International Conference on Developments in Power System Protection, DPSP 2014 - Copenhagen, United Kingdom Duration: 31 Mar 2014 → 3 Apr 2014

Conference

Conference	12th IET International Conference on Developments in Power System Protection, DPSP 2014
Country/Territory	United Kingdom
City	Copenhagen
Period	31/03/14 → 3/04/14

Keywords

DC faults
high voltage direct current transmission
modular multi-level modeling
voltage source converters
power system protection
optimisation techniques
DC transmission

Access to Document

10.1049/cp.2014.0014

Page_etal_DPSP_2014_DC_fault_parameter_sensitivity_analysisAccepted author manuscript, 767 KB

Cite this

@inproceedings{78b349ab294a444194177bab2f767a6e,

title = "DC fault parameter sensitivity analysis",

abstract = "At present High Voltage Direct Current (HVDC) Voltage Source Converters (VSC) are susceptible dc faults leading to extreme currents. The fault current cannot be controlled by the converter switching flows in the anti-parallel diodes. Protection devices are, therefore, required to operate with sufficient speed to avoid device failure. A method is introduced to calculate the critical time for protection to operate. Using this method it is then shown how the critical time may be extended by way of optimization of passive system components. In order to perform this optimization a new post-fault (when the converter gating signals are inhibited) model of the Modular Multi-Level (MMC) converter is introduced which drastically reduces simulation time, allowing high resolution parameter sweeps to be performed. The model is validated and is shown to produce fault characteristics similar to that of a conventional switched model.",

keywords = "DC faults, high voltage direct current transmission, modular multi-level modeling, voltage source converters, power system protection, optimisation techniques, DC transmission",

author = "Frederick Page and Grain Adam and Stephen Finney and Derrick Holliday and Lie Xu",

note = "This paper is a postprint of a paper submitted to and accepted for publication in Proceedings of the 12th IET International Conference on Developments in Power System Protection (DPSP 2014) and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.; 12th IET International Conference on Developments in Power System Protection, DPSP 2014 ; Conference date: 31-03-2014 Through 03-04-2014",

year = "2014",

doi = "10.1049/cp.2014.0014",

language = "English",

isbn = "9781849198349 ",

volume = "2014",

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Page, F, Adam, G, Finney, S, Holliday, D & Xu, L 2014, DC fault parameter sensitivity analysis. in Proceedings of the 12th IET International Conference on Developments in Power System Protection (DPSP 2014). vol. 2014, 3.1.4, Institution of Engineering and Technology, Stevenage, UK, 12th IET International Conference on Developments in Power System Protection, DPSP 2014, Copenhagen, United Kingdom, 31/03/14. https://doi.org/10.1049/cp.2014.0014

DC fault parameter sensitivity analysis. / Page, Frederick; Adam, Grain; Finney, Stephen et al.
Proceedings of the 12th IET International Conference on Developments in Power System Protection (DPSP 2014). Vol. 2014 Stevenage, UK: Institution of Engineering and Technology, 2014. 3.1.4.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

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AU - Page, Frederick

AU - Adam, Grain

AU - Finney, Stephen

AU - Holliday, Derrick

AU - Xu, Lie

N1 - This paper is a postprint of a paper submitted to and accepted for publication in Proceedings of the 12th IET International Conference on Developments in Power System Protection (DPSP 2014) and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.

PY - 2014

Y1 - 2014

N2 - At present High Voltage Direct Current (HVDC) Voltage Source Converters (VSC) are susceptible dc faults leading to extreme currents. The fault current cannot be controlled by the converter switching flows in the anti-parallel diodes. Protection devices are, therefore, required to operate with sufficient speed to avoid device failure. A method is introduced to calculate the critical time for protection to operate. Using this method it is then shown how the critical time may be extended by way of optimization of passive system components. In order to perform this optimization a new post-fault (when the converter gating signals are inhibited) model of the Modular Multi-Level (MMC) converter is introduced which drastically reduces simulation time, allowing high resolution parameter sweeps to be performed. The model is validated and is shown to produce fault characteristics similar to that of a conventional switched model.

AB - At present High Voltage Direct Current (HVDC) Voltage Source Converters (VSC) are susceptible dc faults leading to extreme currents. The fault current cannot be controlled by the converter switching flows in the anti-parallel diodes. Protection devices are, therefore, required to operate with sufficient speed to avoid device failure. A method is introduced to calculate the critical time for protection to operate. Using this method it is then shown how the critical time may be extended by way of optimization of passive system components. In order to perform this optimization a new post-fault (when the converter gating signals are inhibited) model of the Modular Multi-Level (MMC) converter is introduced which drastically reduces simulation time, allowing high resolution parameter sweeps to be performed. The model is validated and is shown to produce fault characteristics similar to that of a conventional switched model.

KW - DC faults

KW - high voltage direct current transmission

KW - modular multi-level modeling

KW - voltage source converters

KW - power system protection

KW - optimisation techniques

KW - DC transmission

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BT - Proceedings of the 12th IET International Conference on Developments in Power System Protection (DPSP 2014)

PB - Institution of Engineering and Technology

CY - Stevenage, UK

T2 - 12th IET International Conference on Developments in Power System Protection, DPSP 2014

Y2 - 31 March 2014 through 3 April 2014

ER -

DC fault parameter sensitivity analysis

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Energy Networks Grand Challenge: Top And Tail Infrastuctures

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DC fault parameter sensitivity analysis

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Conference

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Energy Networks Grand Challenge: Top And Tail Infrastuctures

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