Compact iterative FPGA camellia algorithm implementations

D. Denning, J. Irvine, M. Devlin

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

In this paper we present various iterative Camellia encryption algorithm implementations. The algorithm uses a 128-bit key, which keeps the algorithm as small as possible. The purpose for this implementation is for low-cost or area-restricted implementations suitable for embedded or mobile applications. We discuss the design and implementation considerations for a feedback architecture and achieve a throughput of 426Mbits/sec without key scheduling and 388Mbit/sec with key scheduling.
Original languageEnglish
Pages311-314
Number of pages4
DOIs
Publication statusPublished - Dec 2004
Event3rd International Conference on Field-Programmable Technology - Brisbane, Australia
Duration: 6 Dec 20048 Dec 2004

Conference

Conference3rd International Conference on Field-Programmable Technology
CountryAustralia
CityBrisbane
Period6/12/048/12/04

Keywords

  • compact
  • iterative fpga
  • camellia algorithm
  • implementations
  • cryptography
  • throughput
  • scheduling
  • public key
  • portfolios
  • iterative algorithms
  • field programmable gate arrays
  • feedback
  • electronic government
  • digital signatures

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  • Cite this

    Denning, D., Irvine, J., & Devlin, M. (2004). Compact iterative FPGA camellia algorithm implementations. 311-314. Paper presented at 3rd International Conference on Field-Programmable Technology , Brisbane, Australia. https://doi.org/10.1109/FPT.2004.1393287