Coarse angle rotation mode CORDIC based single processing element QR-RLS processor

Over the last 30 years Digital Signal Processing algorithm implementation has been driven by the continued progress and availability of high speed ASIC circuit technology. The classic method of CORDIC (Coordinate Rotation by Digital
Computer) arithmetic has been widely implemented as part of the computational requirements of the well known QR-RLS (recursive least squares) algorithm. In this paper we propose a new modified version of the CORDIC that features
a single processor element that is easily pipelinable and can be used to implement both the Givens generations and Givens rotations associated with the QR update. Using a Xilinx FPGA for implementaton results show that this proposed structure requires less resources and produces a more regular and therefore lower cost structure than other equivalent methods recently presented.