TY - GEN
T1 - Bit error rate performance evaluation of a silicon-on-insulator optical-network-on-chip router in a WDM configuration
AU - Parini, Alberto
AU - Bellanca, Gaetano
AU - Annoni, Andrea
AU - Morichetti, Francesco
AU - Melloni, Andrea
AU - Strain, Michael John
AU - Sorel, Marc
AU - Pareige, Christelle
AU - Gay, Mathilde
AU - Bramerie, Laurent
AU - Thual, Monique
PY - 2013/12/1
Y1 - 2013/12/1
N2 - We present a microring-based integrated router in Silicon-on-Insulator technology suitable for optical networking at chip level. The switching functionalities in a 3-channels 10 Gbit/s WDM configuration are evaluated through the BER curves. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.
AB - We present a microring-based integrated router in Silicon-on-Insulator technology suitable for optical networking at chip level. The switching functionalities in a 3-channels 10 Gbit/s WDM configuration are evaluated through the BER curves. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.
KW - 3-channel WDM configuration
KW - BER curves
KW - bit error rate performance evaluation
KW - microring-based integrated router
UR - http://www.scopus.com/inward/record.url?scp=84893422028&partnerID=8YFLogxK
U2 - 10.1049/cp.2013.1572
DO - 10.1049/cp.2013.1572
M3 - Conference contribution book
AN - SCOPUS:84893422028
SN - 9781849197595
VL - 2013
SP - 897
EP - 899
BT - 39th European Conference and Exhibition on Optical Communication (ECOC 2013)
ER -