Bit error rate performance evaluation of a silicon-on-insulator optical-network-on-chip router in a WDM configuration

Alberto Parini, Gaetano Bellanca, Andrea Annoni, Francesco Morichetti, Andrea Melloni, Michael John Strain, Marc Sorel, Christelle Pareige, Mathilde Gay, Laurent Bramerie, Monique Thual

Research output: Chapter in Book/Report/Conference proceedingConference contribution book


We present a microring-based integrated router in Silicon-on-Insulator technology suitable for optical networking at chip level. The switching functionalities in a 3-channels 10 Gbit/s WDM configuration are evaluated through the BER curves. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.
Original languageEnglish
Title of host publication39th European Conference and Exhibition on Optical Communication (ECOC 2013)
Number of pages3
Publication statusPublished - 1 Dec 2013


  • 3-channel WDM configuration
  • BER curves
  • bit error rate performance evaluation
  • microring-based integrated router

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