Automatic FFT code generation for FPGA with high flexibility and human readability

John O'Sullivan, Stephan Weiss, Garrey Rice

Research output: Chapter in Book/Report/Conference proceedingConference contribution book

Abstract

This paper describes a Fast Fourier Transform (FFT) core which uses code generation to create optimised Hardware Description Language (HDL) code for a radix-2, decimation in time FFT. The generated code is designed to be human readable, vendor non-specific and is available in both Verilog and VHDL languages. A choice of In-place or Multipath Delay Commutator (MDC) architectures is provided. Selectable architectures and generic, readable HDL code make the core highly flexible for use in different applications and with different hardware platforms. The implementation of the available architectures and their relative merits are discussed. Maximum clock speed and resource requirements are examined and compared.
Original languageEnglish
Title of host publicationConference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011
PublisherIEEE
Pages2197-2201
Number of pages5
ISBN (Print)978-1-4673-0321-7
DOIs
Publication statusPublished - Nov 2011
Event45th Asilomar Conference on Signals, Systems, and Computers - Pacific Grove, CA, United States
Duration: 6 Nov 20119 Nov 2011

Conference

Conference45th Asilomar Conference on Signals, Systems, and Computers
CountryUnited States
CityPacific Grove, CA
Period6/11/119/11/11

Keywords

  • digital arithmetic
  • fast Fourier transforms
  • field programmable gate arrays
  • hardware design languages

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  • Cite this

    O'Sullivan, J., Weiss, S., & Rice, G. (2011). Automatic FFT code generation for FPGA with high flexibility and human readability. In Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011 (pp. 2197-2201 ). IEEE. https://doi.org/10.1109/ACSSC.2011.6190421