Automatic FFT code generation for FPGA with high flexibility and human readability

John  O'Sullivan; Stephan Weiss; Garrey Rice

doi:10.1109/ACSSC.2011.6190421

Automatic FFT code generation for FPGA with high flexibility and human readability

John O'Sullivan, Stephan Weiss, Garrey Rice

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

Abstract

This paper describes a Fast Fourier Transform (FFT) core which uses code generation to create optimised Hardware Description Language (HDL) code for a radix-2, decimation in time FFT. The generated code is designed to be human readable, vendor non-specific and is available in both Verilog and VHDL languages. A choice of In-place or Multipath Delay Commutator (MDC) architectures is provided. Selectable architectures and generic, readable HDL code make the core highly flexible for use in different applications and with different hardware platforms. The implementation of the available architectures and their relative merits are discussed. Maximum clock speed and resource requirements are examined and compared.

Original language	English
Title of host publication	Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011
Publisher	IEEE
Pages	2197-2201
Number of pages	5
ISBN (Print)	978-1-4673-0321-7
DOIs	https://doi.org/10.1109/ACSSC.2011.6190421
Publication status	Published - Nov 2011
Event	45th Asilomar Conference on Signals, Systems, and Computers - Pacific Grove, CA, United States Duration: 6 Nov 2011 → 9 Nov 2011

Conference

Conference	45th Asilomar Conference on Signals, Systems, and Computers
Country/Territory	United States
City	Pacific Grove, CA
Period	6/11/11 → 9/11/11

Keywords

digital arithmetic
fast Fourier transforms
field programmable gate arrays
hardware design languages

Access to Document

10.1109/ACSSC.2011.6190421

Cite this

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title = "Automatic FFT code generation for FPGA with high flexibility and human readability",

abstract = "This paper describes a Fast Fourier Transform (FFT) core which uses code generation to create optimised Hardware Description Language (HDL) code for a radix-2, decimation in time FFT. The generated code is designed to be human readable, vendor non-specific and is available in both Verilog and VHDL languages. A choice of In-place or Multipath Delay Commutator (MDC) architectures is provided. Selectable architectures and generic, readable HDL code make the core highly flexible for use in different applications and with different hardware platforms. The implementation of the available architectures and their relative merits are discussed. Maximum clock speed and resource requirements are examined and compared.",

keywords = "digital arithmetic, fast Fourier transforms, field programmable gate arrays, hardware design languages ",

author = "John O'Sullivan and Stephan Weiss and Garrey Rice",

year = "2011",

month = nov,

doi = "10.1109/ACSSC.2011.6190421",

language = "English",

isbn = "978-1-4673-0321-7",

pages = "2197--2201 ",

booktitle = "Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011",

publisher = "IEEE",

note = "45th Asilomar Conference on Signals, Systems, and Computers ; Conference date: 06-11-2011 Through 09-11-2011",

}

O'Sullivan, J, Weiss, S & Rice, G 2011, Automatic FFT code generation for FPGA with high flexibility and human readability. in Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011. IEEE, pp. 2197-2201 , 45th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, United States, 6/11/11. https://doi.org/10.1109/ACSSC.2011.6190421

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T1 - Automatic FFT code generation for FPGA with high flexibility and human readability

AU - O'Sullivan, John

AU - Weiss, Stephan

AU - Rice, Garrey

PY - 2011/11

Y1 - 2011/11

N2 - This paper describes a Fast Fourier Transform (FFT) core which uses code generation to create optimised Hardware Description Language (HDL) code for a radix-2, decimation in time FFT. The generated code is designed to be human readable, vendor non-specific and is available in both Verilog and VHDL languages. A choice of In-place or Multipath Delay Commutator (MDC) architectures is provided. Selectable architectures and generic, readable HDL code make the core highly flexible for use in different applications and with different hardware platforms. The implementation of the available architectures and their relative merits are discussed. Maximum clock speed and resource requirements are examined and compared.

AB - This paper describes a Fast Fourier Transform (FFT) core which uses code generation to create optimised Hardware Description Language (HDL) code for a radix-2, decimation in time FFT. The generated code is designed to be human readable, vendor non-specific and is available in both Verilog and VHDL languages. A choice of In-place or Multipath Delay Commutator (MDC) architectures is provided. Selectable architectures and generic, readable HDL code make the core highly flexible for use in different applications and with different hardware platforms. The implementation of the available architectures and their relative merits are discussed. Maximum clock speed and resource requirements are examined and compared.

KW - digital arithmetic

KW - fast Fourier transforms

KW - field programmable gate arrays

KW - hardware design languages

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U2 - 10.1109/ACSSC.2011.6190421

DO - 10.1109/ACSSC.2011.6190421

M3 - Conference contribution book

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SP - 2197

EP - 2201

BT - Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011

PB - IEEE

T2 - 45th Asilomar Conference on Signals, Systems, and Computers

Y2 - 6 November 2011 through 9 November 2011

ER -

Automatic FFT code generation for FPGA with high flexibility and human readability

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Keywords

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