Abstract
DSP system-level design decisions can have significant effects on Field Programmable Gate Array (FPGA) hardware cost and efficiency. In this paper we demonstrate how modifymg filter coefficients and taking advantage of non-canonical implementation techniques can yield reduced FPGA hardware cost. Using the Root-Raised Cosine (RRC) pulse shaping filters required in the 3G uplink reception chain as an example, different implementation techniques are compared in terms of DSP system performance and FPGA cost. RRC filter
performance is evaluated through simulation of the Adjacent Channel Selectivity (ACS) test. Simulation results are presented and the differing hardware structures are evaluated.
performance is evaluated through simulation of the Adjacent Channel Selectivity (ACS) test. Simulation results are presented and the differing hardware structures are evaluated.
| Original language | English |
|---|---|
| Number of pages | 5 |
| Publication status | Published - May 2002 |
| Event | 3rd International Conference on 3G Mobile Communications Technologies - London, United Kingdom Duration: 8 May 2002 → 10 May 2002 |
Conference
| Conference | 3rd International Conference on 3G Mobile Communications Technologies |
|---|---|
| Country | United Kingdom |
| City | London |
| Period | 8/05/02 → 10/05/02 |
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Keywords
- 3G
- field programmable gate array
- filter coefficients
- root-raised cosine
Cite this
MacPherson, K. N., Stirling, I. G., Rice, G., Garcia-Alis, D., & Stewart, R. W. (2002). Arithmetic implementation techniques and methodologies for 3G uplink reception in Xilinx FPGAs. Paper presented at 3rd International Conference on 3G Mobile Communications Technologies, London, United Kingdom.