Abstract
In this paper, we present a Gigabit Ethernet AES (Advanced Encription Standard) Encription Engine. One of the main push factors in software-defined radio(SDR) is the use of programinable devices such as field programmable gate arrays (FPGAs) or digital a signal processors (DSPs). Including such devices in SDR base station systems allows for reconfiguration and upgrade of the communication system and the application processing. Due to the increased concerns regarding secure information, we have implemented an AES encryption engine for data processing in a SDR system using one of the latest FPGAs available. The engine is capable of simultaneously processing 2 input and 2 output data streams of 1 Gigabit each. As the system has been developed on an inchistrial scalable architecture, a further 3 FPGA daughter cards can be added to the board for further application processing, and each board could be one of many.
| Original language | English |
|---|---|
| Pages | 1963-1967 |
| Number of pages | 5 |
| DOIs | |
| Publication status | Published - Sept 2004 |
| Event | 60th IEEE Vehicular Technology Conference - Los Angeles, United States Duration: 26 Sept 2004 → 29 Sept 2004 |
Conference
| Conference | 60th IEEE Vehicular Technology Conference |
|---|---|
| Country/Territory | United States |
| City | Los Angeles |
| Period | 26/09/04 → 29/09/04 |
Keywords
- implementation
- gigabit ethernet
- aes encryption engine
- application processing
- sdr
- application software
- logic devices
- hardware
- field programmable gate arrays
- ethernet networks
- engines
- digital signal processing , Digital signal processors
- cryptography
- computer architecture