An FPGA implementation of pattern-selective pyramidal image fusion

Oliver Sims; James Irvine

doi:10.1109/FPL.2006.311296

An FPGA implementation of pattern-selective pyramidal image fusion

Oliver Sims, James Irvine

Electronic And Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution book

12 Citations (Scopus)

Abstract

The aim of image fusion is to combine multiple images (from one or more sensors) into a single composite image that retains all useful data without introducing artefacts. Pattern-selective techniques attempt to identify and extract whole features in the source images to use in the composite. These techniques usually rely on multiresolution image representations such as Gaussian pyramids, which are localised in both the spatial and spatial-frequency domains, since they enable identification of features at many scales simultaneously. This paper presents an FPGA implementation of pyramidal decomposition and subsequent fusion of dual video streams. This is the first reported instance of a hardware implementation of pattern-selective pyramidal image fusion. Use of FPGA technology has enabled a design that can fuse dual video streams (greyscale VGA, 30fps) in real-time, and provides approximately 100 times speedup over a 2.8GHz Pentium-4

Original language	English
Title of host publication	2006 International Conference on Field Programmable Logic and Applications, Proceedings
Editors	A Koch, P Leong, A Koch
Place of Publication	New York
Publisher	IEEE
Pages	709-712
Number of pages	4
ISBN (Print)	9781424403127, 142440312X
DOIs	https://doi.org/10.1109/FPL.2006.311296
Publication status	Published - 16 May 2007
Event	16th International Conference on Field Programmable Logic and Applications - Madrid, Spain Duration: 28 Aug 2006 → 30 Aug 2006

Conference

Conference	16th International Conference on Field Programmable Logic and Applications
Abbreviated title	FPL 2006
Country/Territory	Spain
City	Madrid
Period	28/08/06 → 30/08/06

Keywords

field programmable gate arrays
image fusion
video streaming
data mining
feature extraction
image representation

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10.1109/FPL.2006.311296

Cite this

@inproceedings{d95de7f36fd24172ac3abc7706c47bc3,

title = "An FPGA implementation of pattern-selective pyramidal image fusion",

abstract = "The aim of image fusion is to combine multiple images (from one or more sensors) into a single composite image that retains all useful data without introducing artefacts. Pattern-selective techniques attempt to identify and extract whole features in the source images to use in the composite. These techniques usually rely on multiresolution image representations such as Gaussian pyramids, which are localised in both the spatial and spatial-frequency domains, since they enable identification of features at many scales simultaneously. This paper presents an FPGA implementation of pyramidal decomposition and subsequent fusion of dual video streams. This is the first reported instance of a hardware implementation of pattern-selective pyramidal image fusion. Use of FPGA technology has enabled a design that can fuse dual video streams (greyscale VGA, 30fps) in real-time, and provides approximately 100 times speedup over a 2.8GHz Pentium-4",

keywords = "field programmable gate arrays, image fusion, video streaming , data mining , feature extraction , image representation ",

author = "Oliver Sims and James Irvine",

year = "2007",

month = may,

day = "16",

doi = "10.1109/FPL.2006.311296",

language = "English",

isbn = "9781424403127",

pages = "709--712 ",

editor = "A Koch and P Leong and Koch, {A }",

booktitle = "2006 International Conference on Field Programmable Logic and Applications, Proceedings",

publisher = "IEEE",

note = "16th International Conference on Field Programmable Logic and Applications, FPL 2006 ; Conference date: 28-08-2006 Through 30-08-2006",

}

Sims, O & Irvine, J 2007, An FPGA implementation of pattern-selective pyramidal image fusion. in A Koch, P Leong & A Koch (eds), 2006 International Conference on Field Programmable Logic and Applications, Proceedings . IEEE, New York, pp. 709-712 , 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, 28/08/06. https://doi.org/10.1109/FPL.2006.311296

TY - GEN

T1 - An FPGA implementation of pattern-selective pyramidal image fusion

AU - Sims, Oliver

AU - Irvine, James

PY - 2007/5/16

Y1 - 2007/5/16

N2 - The aim of image fusion is to combine multiple images (from one or more sensors) into a single composite image that retains all useful data without introducing artefacts. Pattern-selective techniques attempt to identify and extract whole features in the source images to use in the composite. These techniques usually rely on multiresolution image representations such as Gaussian pyramids, which are localised in both the spatial and spatial-frequency domains, since they enable identification of features at many scales simultaneously. This paper presents an FPGA implementation of pyramidal decomposition and subsequent fusion of dual video streams. This is the first reported instance of a hardware implementation of pattern-selective pyramidal image fusion. Use of FPGA technology has enabled a design that can fuse dual video streams (greyscale VGA, 30fps) in real-time, and provides approximately 100 times speedup over a 2.8GHz Pentium-4

AB - The aim of image fusion is to combine multiple images (from one or more sensors) into a single composite image that retains all useful data without introducing artefacts. Pattern-selective techniques attempt to identify and extract whole features in the source images to use in the composite. These techniques usually rely on multiresolution image representations such as Gaussian pyramids, which are localised in both the spatial and spatial-frequency domains, since they enable identification of features at many scales simultaneously. This paper presents an FPGA implementation of pyramidal decomposition and subsequent fusion of dual video streams. This is the first reported instance of a hardware implementation of pattern-selective pyramidal image fusion. Use of FPGA technology has enabled a design that can fuse dual video streams (greyscale VGA, 30fps) in real-time, and provides approximately 100 times speedup over a 2.8GHz Pentium-4

KW - field programmable gate arrays

KW - image fusion

KW - video streaming

KW - data mining

KW - feature extraction

KW - image representation

U2 - 10.1109/FPL.2006.311296

DO - 10.1109/FPL.2006.311296

M3 - Conference contribution book

SN - 9781424403127

SN - 142440312X

SP - 709

EP - 712

BT - 2006 International Conference on Field Programmable Logic and Applications, Proceedings

A2 - Koch, A

A2 - Leong, P

A2 - Koch, A

PB - IEEE

CY - New York

T2 - 16th International Conference on Field Programmable Logic and Applications

Y2 - 28 August 2006 through 30 August 2006

ER -

An FPGA implementation of pattern-selective pyramidal image fusion

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Keywords

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