Adaptive-Filter PMU Hardware Validation to IEEE C37.118.1a Requirements: Strathclyde ENG52 REG D6 Report

This report documents the implementation and testing of a hardware Phasor Measurement Unit (PMU) prototype, using a Beckhoff-based hardware platform. This platform offers several convenient features for PMU development, such as hardware modularity, support for integrating C++ and Simulink models, IEEE 1588 support, and scalability to multiple measurement locations. The Strathclyde M-class PMU algorithm can be deployed on this platform requiring less than 8% of the CPU time of a single CPU core, with 10 kHz analogue sampling.

A closed-loop testing procedure, using RTDS hardware and software, has been used to quantify the performance of the Strathclyde PMU algorithm. With proper calibration of the analogue system, as would be the case for a PMU to be deployed in the field, the PMU can achieve relatively low error metrics according to the Synchrophasor standard requirements. For example, for the “static” PMU tests, Total Vector Error (TVE) values as low as 0.01% can be achieved (where the Synchrophasor standard requires a maximum TVE of 1%).

Additional tests with multiple disturbances and with emulation of a power system fault have been conducted to demonstrate that PMU algorithms require resilience under realistic worst-case scenarios – and to make a case for testing all PMUs in this way.

A new method has been devised for accurately and conveniently characterising the reporting latency of PMUs. This method can also be used to measure the end-to-end performance of transmitting PMU data over wide-area communications networks, thereby providing more accurate knowledge of the actual latency of the measurement systems used to implement novel power system control and protection schemes.

The algorithm will be integrated within Synaptec’s passive and distributed optical sensing platform for wide area synchrophasor-based monitoring, protection, and control.