A two-stage interpolation time-to-digital converter implemented in 20 nm and 28 nm FGPAs

Yu Wang, Wujun Xie, Haochang Chen, Chengquan Pei, David Day-Uei Li

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This article presents a two-stage interpolation time- to-digital converter (TDC), combining a Vernier gray code oscillator TDC (VGCO-TDC) and a tapped-delay line TDC (TDL- TDC). The proposed TDC uses the Nutt method to achieve a broad, high-resolution measurement range. It utilizes look-up tables (LUTs)-based gray code oscillators (GCOs) to build a VGCO-TDC as the first-stage interpolation for fine-time measurements. Then the overtaking residual from the VGCO-TDC is measured by a TDL-TDC to achieve the second-stage interpolation. Due to the two-stage interpolation architecture, the carry-chain-based delay line only needs to cover the resolution of the VGCO-TDC. Hence, we can reduce the delay-line length and related hardware resource utilization. We implemented and evaluated a 16-channel TDC system in Xilinx 20-nm Kintex-UltraScale and 28-nm Virtex-7 field-programmable gate arrays (FPGAs). The Kintex-UltraScale version achieves an average resolution (least significant bit, LSB) of 4.57 picoseconds (ps) with 4.36 LSB average peak-to-peak differential nonlinearity (DNLpk-pk). The Virtex-7 version achieves an average resolution of 10.05 ps with 2.85 LSB average DNLpk-pk
Original languageEnglish
Number of pages12
JournalIEEE Transactions on Industrial Electronics
Publication statusAccepted/In press - 15 Feb 2024


  • two-stage interpolation
  • hybrid time-to-digital converter
  • field-programmable gare array
  • low hardware utilization


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