### Abstract

Language | English |
---|---|

Pages | 2332-2343 |

Number of pages | 12 |

Journal | IEEE Transactions on Industrial Electronics |

Volume | 57 |

Issue number | 7 |

DOIs | |

Publication status | Published - 2010 |

### Fingerprint

### Keywords

- capacitors
- drives
- invertors
- switching

### Cite this

*IEEE Transactions on Industrial Electronics*,

*57*(7), 2332-2343. https://doi.org/10.1109/TIE.2009.2033087

}

*IEEE Transactions on Industrial Electronics*, vol. 57, no. 7, pp. 2332-2343. https://doi.org/10.1109/TIE.2009.2033087

**A space vector switching strategy for three-level five-phase inverter drives.** / Gao, L.; Fletcher, J.E.

Research output: Contribution to journal › Article

TY - JOUR

T1 - A space vector switching strategy for three-level five-phase inverter drives

AU - Gao, L.

AU - Fletcher, J.E.

PY - 2010

Y1 - 2010

N2 - A novel space vector modulation (SVM) technique for a three-level five-phase inverter is described based on an optimized five vectors concept. The concept utilizes a novel vector minimization technique that reduces the number of vectors in the d1-q1 vector space by identifying candidate vectors in each of the ten sectors that comprise the decagon vector space. The candidate vectors are selected based on the inequality relationship between the five-phase voltages during each switching cycle. Using this technique, the original 243 inverter states are reduced to 113 candidate vectors, and from the remaining states ten possible switching sequences in each sector are utilized to develop the desired voltage reference in the d1-q1 vector space while forcing a null vector in the d3-q3 vector space. A novel region determination technique is also introduced to identify the subregion that the d1-q1 voltage vector occupies. This technique significantly reduces the computational overhead required when implementing SVM techniques with multilevel and multiphase inverters. The space vector technique can utilize redundant vectors to assist in balancing subcycle variation of the dc-link capacitor voltage under unbalanced load conditions. Experiments validate simulation results where the low-order voltage harmonics show that the d3-q3 voltage vector is null.

AB - A novel space vector modulation (SVM) technique for a three-level five-phase inverter is described based on an optimized five vectors concept. The concept utilizes a novel vector minimization technique that reduces the number of vectors in the d1-q1 vector space by identifying candidate vectors in each of the ten sectors that comprise the decagon vector space. The candidate vectors are selected based on the inequality relationship between the five-phase voltages during each switching cycle. Using this technique, the original 243 inverter states are reduced to 113 candidate vectors, and from the remaining states ten possible switching sequences in each sector are utilized to develop the desired voltage reference in the d1-q1 vector space while forcing a null vector in the d3-q3 vector space. A novel region determination technique is also introduced to identify the subregion that the d1-q1 voltage vector occupies. This technique significantly reduces the computational overhead required when implementing SVM techniques with multilevel and multiphase inverters. The space vector technique can utilize redundant vectors to assist in balancing subcycle variation of the dc-link capacitor voltage under unbalanced load conditions. Experiments validate simulation results where the low-order voltage harmonics show that the d3-q3 voltage vector is null.

KW - capacitors

KW - drives

KW - invertors

KW - switching

U2 - 10.1109/TIE.2009.2033087

DO - 10.1109/TIE.2009.2033087

M3 - Article

VL - 57

SP - 2332

EP - 2343

JO - IEEE Transactions on Industrial Electronics

T2 - IEEE Transactions on Industrial Electronics

JF - IEEE Transactions on Industrial Electronics

SN - 0278-0046

IS - 7

ER -