A simple technique to optimize SiC device selection for minimum loss

SiC devices are now achieving voltage and current ratings which challenge applications previously dominated by IGBTs. Unlike with IGBTs parallel connection of SiC devices may be used to reduce conduction losses. SiC conduction loss is reduced with low Rds(on), or large die area, while switching loss reduction requires small Coss, and small die area. An improved analytical model is presented to accurately predict SiC switching loss. Extensive experimental data is used to verify the accuracy of the model for two different SiC devices. This paper then presents a simple technique for identifying optimum Rds(on) at a given switching frequency using a Figure of Merit (FOM) for SiC. The FOM is then used in a simple model to approximate SiC losses and is combined with a simple filter model to attempt to identify optimum switching frequency, and this is compared with the full model. It is shown that the FOM model comes close to predicting optimum switching frequency, but the full model must be used to accurately pinpoint optimum switching frequency. The FOM technique therefore has value in identifying optimum die area and device choice so that the full, more complex model need only be implemented once.